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soc/intel/apollolake: add offset of GPIO_TIER1_SCI_EN bit 

This patch adds the support for gpio_tier1_sci_en bit which
needs to be set before going to sleep so that when
gpio_tier1_sci_sts bit gets set platform can wake
from S3.

BUG = chrome-os-partner:53992
TEST = Platform wakes from S3 on lidopen,key press.
       Tested on Amenia and Reef boards.

Change-Id: I3ba79fa53ca8817149d585fa795a8f427c128dcb
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/15612
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Shaunak Saha 2016-07-11 16:03:52 -07:00 committed by Aaron Durbin
parent 81d1e09113
commit 0cf11cb783
1 changed files with 5 additions and 0 deletions
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5
src/soc/intel/apollolake/include/soc/pm.h
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@ -119,6 +119,11 @@
#define GPE0_STS(x) (0x20 + (x * 4)) #define GPE0_STS(x) (0x20 + (x * 4))
#define GPE0_EN(x) (0x30 + (x * 4)) #define GPE0_EN(x) (0x30 + (x * 4))
#define PME_B0_EN (1 << 13) #define PME_B0_EN (1 << 13)
/*
* Enables the setting of the GPIO_TIER1_SCI_STS bit to generate a wake event
* and/or an SCI or SMI#.
*/
#define GPIO_TIER_1_SCI (1 << 15)
/* Memory mapped IO registers behind PMC_BASE_ADDRESS */ /* Memory mapped IO registers behind PMC_BASE_ADDRESS */
#define PRSTS 0x1000 #define PRSTS 0x1000