purism/librem_bdl: Add support for Librem 15 v2
Adding new librem_bdl variant for the Librem 15 v2, which is very similar to Librem 13 v1, with the following differences: - SATA ports 0 and 1 instead of 0 and 3 - SATA DTLE IOBP value is 7 instead of 9 for port 0 - There is no LAN device - There are two SODIMM slots, and DQs are interleaved - USB ports are different Change-Id: Ifaca382a540d085e6c919daa992a0fbd52643a5b Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/26184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Youness Alaoui
Patrick Georgi
parent
b799e0df3d
commit
0cf89bf20a
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@ -13,10 +13,12 @@ if BOARD_PURISM_BASEBOARD_LIBREM_BDL
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config VARIANT_DIR
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string
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default "librem13v1" if BOARD_PURISM_LIBREM13_V1
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default "librem15v2" if BOARD_PURISM_LIBREM15_V2
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config DEVICETREE
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string
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default "variants/librem13v1/devicetree.cb" if BOARD_PURISM_LIBREM13_V1
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default "variants/librem15v2/devicetree.cb" if BOARD_PURISM_LIBREM15_V2
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config DRIVERS_PS2_KEYBOARD
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def_bool y
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@ -54,14 +56,17 @@ config MAINBOARD_VENDOR
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config MAINBOARD_PART_NUMBER
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string
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default "Librem 13 v1" if BOARD_PURISM_LIBREM13_V1
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default "Librem 15 v2" if BOARD_PURISM_LIBREM15_V2
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config MAINBOARD_FAMILY
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string
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default "Librem 13" if BOARD_PURISM_LIBREM13_V1
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default "Librem 15" if BOARD_PURISM_LIBREM15_V2
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config MAINBOARD_VERSION
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string
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default "1.0" if BOARD_PURISM_LIBREM13_V1
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default "2.0" if BOARD_PURISM_LIBREM15_V2
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config MAX_CPUS
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int
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@ -79,6 +84,8 @@ config PRE_GRAPHICS_DELAY
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config VGA_BIOS_ID
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string
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default "8086,1616"
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default "8086,1616" if BOARD_PURISM_LIBREM13_V1
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default "8086,162b" if BOARD_PURISM_LIBREM15_V2
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endif
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@ -1,3 +1,7 @@
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config BOARD_PURISM_LIBREM13_V1
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bool "Librem 13 v1"
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select BOARD_PURISM_BASEBOARD_LIBREM_BDL
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config BOARD_PURISM_LIBREM15_V2
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bool "Librem 15 v2"
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select BOARD_PURISM_BASEBOARD_LIBREM_BDL
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@ -0,0 +1,9 @@
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Category: laptop
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Vendor name: Purism
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Board name: Librem 15 v2
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Board URL: https://web.archive.org/web/20160529052744/https://puri.sm/librem-15/
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ROM package: SOIC8
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ROM protocol: SPI
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ROM socketed: n
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Flashrom support: y
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Release year: 2015
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@ -0,0 +1,75 @@
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chip soc/intel/broadwell
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# Enable eDP Hotplug with 6ms pulse
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register "gpu_dp_d_hotplug" = "0x06"
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# Enable DDI1 Hotplug with 6ms pulse
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register "gpu_dp_b_hotplug" = "0x06"
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# Set backlight PWM values for eDP
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register "gpu_cpu_backlight" = "0x00000200"
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register "gpu_pch_backlight" = "0x04000200"
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# Enable Panel and configure power delays
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register "gpu_panel_port_select" = "1" # eDP
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register "gpu_panel_power_cycle_delay" = "6" # 500ms
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register "gpu_panel_power_up_delay" = "2000" # 200ms
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register "gpu_panel_power_down_delay" = "500" # 50ms
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register "gpu_panel_power_backlight_on_delay" = "2000" # 200ms
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register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms
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# EC host command ranges are in 0x380-0x383 & 0x80-0x8f
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register "gen1_dec" = "0x00000381"
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register "gen2_dec" = "0x000c0081"
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# Port 0 is HDD
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# Port 1 is M.2 NGFF
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register "sata_port_map" = "0x3"
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# Port tuning for link stability
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register "sata_port0_gen3_dtle" = "7"
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register "sata_port1_gen3_dtle" = "9"
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register "sata_port2_gen3_dtle" = "9"
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register "sata_port3_gen3_dtle" = "7"
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device domain 0 on
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device pci 00.0 on end # host bridge
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device pci 02.0 on end # vga controller
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device pci 03.0 on end # mini-hd audio
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device pci 13.0 off end # Smart Sound Audio DSP
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device pci 14.0 on end # USB3 XHCI
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device pci 15.0 off end # Serial I/O DMA
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device pci 15.1 off end # I2C0
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device pci 15.2 off end # I2C1
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device pci 15.3 off end # GSPI0
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device pci 15.4 off end # GSPI1
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device pci 15.5 off end # UART0
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device pci 15.6 off end # UART1
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device pci 16.0 off end # Management Engine Interface 1
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.3 off end # Management Engine KT
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device pci 17.0 off end # SDIO
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device pci 19.0 off end # GbE
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device pci 1b.0 on end # High Definition Audio
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device pci 1c.0 on end # PCIe Port #1
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device pci 1c.1 off end # PCIe Port #2
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device pci 1c.2 off end # PCIe Port #3 - LAN
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device pci 1c.3 on end # PCIe Port #4 - WiFi
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device pci 1c.4 on end # PCIe Port #5
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device pci 1c.5 on end # PCIe Port #6 - M.2 NVMe
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device pci 1d.0 on end # USB2 EHCI
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device pci 1e.0 off end # PCI bridge
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device pci 1f.0 on
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chip ec/purism/librem
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device pnp 0c09.0 on end
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end
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end # LPC bridge
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device pci 1f.2 on end # SATA Controller
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device pci 1f.3 on end # SMBus
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device pci 1f.6 off end # Thermal
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end
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end
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@ -0,0 +1,64 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2016 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <soc/pei_data.h>
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#include <soc/pei_wrapper.h>
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void mainboard_fill_pei_data(struct pei_data *pei_data)
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{
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pei_data->ec_present = 1;
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pei_data->dq_pins_interleaved = 1;
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/* One DIMM slot */
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pei_data->dimm_channel0_disabled = 2;
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pei_data->dimm_channel1_disabled = 2;
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pei_data->spd_addresses[0] = 0xa0;
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pei_data->spd_addresses[2] = 0xa4;
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/* P1: Right Side Port (USB2) */
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pei_data_usb2_port(pei_data, 0, 0x0080, 1, USB_OC_PIN_SKIP,
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USB_PORT_BACK_PANEL);
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/* P2: Right Side Port (USB2) */
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pei_data_usb2_port(pei_data, 1, 0x0080, 1, USB_OC_PIN_SKIP,
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USB_PORT_BACK_PANEL);
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/* P3: Left Side Port (USB2 only) */
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pei_data_usb2_port(pei_data, 2, 0x0080, 1, USB_OC_PIN_SKIP,
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USB_PORT_BACK_PANEL);
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/* P4: Left Side Port (USB2 only) */
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pei_data_usb2_port(pei_data, 3, 0x0080, 1, USB_OC_PIN_SKIP,
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USB_PORT_BACK_PANEL);
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/* P5: Empty */
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pei_data_usb2_port(pei_data, 4, 0x0080, 0, USB_OC_PIN_SKIP,
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USB_PORT_BACK_PANEL);
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/* P6: Bluetooth */
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pei_data_usb2_port(pei_data, 5, 0x0080, 1, USB_OC_PIN_SKIP,
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USB_PORT_SKIP);
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/* P7: Camera */
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pei_data_usb2_port(pei_data, 6, 0x0080, 1, USB_OC_PIN_SKIP,
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USB_PORT_SKIP);
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/* P8: SD Card */
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pei_data_usb2_port(pei_data, 7, 0x0080, 1, USB_OC_PIN_SKIP,
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USB_PORT_BACK_PANEL);
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/* P1: Right Side Port (USB3) */
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pei_data_usb3_port(pei_data, 0, 1, USB_OC_PIN_SKIP, 0);
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/* P2: Right Side Port (USB3) */
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pei_data_usb3_port(pei_data, 1, 1, USB_OC_PIN_SKIP, 0);
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/* P3: Empty */
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pei_data_usb3_port(pei_data, 2, 0, USB_OC_PIN_SKIP, 0);
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/* P4: Empty */
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pei_data_usb3_port(pei_data, 3, 0, USB_OC_PIN_SKIP, 0);
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}
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