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src/soc/intel/apollolake: move TCO1 disable into bootblock 

Cr50 reset processing could take long time, up to 30 s in the worst
case. The TCO watchdog needs to be disabled before Cr50 driver starts,
let's disable it in bootblock.

BRANCH=none
BUG=b:65867313, b:68729265
TEST=verified that resetting the device while keys are being generated
     by the TPM does not cause falling into recovery.

Change-Id: Iaf1f97924590163e45bcac667b6c607503cc8b87
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/22553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Vadim Bendebury 2017-11-20 16:18:45 -08:00
parent f1eb0ea537
commit 0d0408ad4f
2 changed files with 7 additions and 11 deletions
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7
src/soc/intel/apollolake/bootblock/bootblock.c
View File

@ -89,6 +89,8 @@ static void enable_pmcbar(void)
void bootblock_soc_early_init(void)
{
uint32_t reg;
enable_pmcbar();
/* Clear global reset promotion bit */
@ -109,4 +111,9 @@ void bootblock_soc_early_init(void)
/* Initialize GPE for use as interrupt status */
pmc_gpe_init();
/* Stop TCO timer */
reg = inl(ACPI_BASE_ADDRESS + TCO1_CNT);
reg |= TCO_TMR_HLT;
outl(reg, ACPI_BASE_ADDRESS + TCO1_CNT);
}

11
src/soc/intel/apollolake/romstage.c
View File

@ -99,16 +99,6 @@ static void soc_early_romstage_init(void)
lpc_io_setup_comm_a_b();
}
static void disable_watchdog(void)
{
uint32_t reg;
/* Stop TCO timer */
reg = inl(ACPI_BASE_ADDRESS + TCO1_CNT);
reg |= TCO_TMR_HLT;
outl(reg, ACPI_BASE_ADDRESS + TCO1_CNT);
}
/*
* Punit Initialization code. This all isn't documented, but
* this is the recipe.
@ -202,7 +192,6 @@ asmlinkage void car_stage_entry(void)
timestamp_add_now(TS_START_ROMSTAGE);
soc_early_romstage_init();
disable_watchdog();
console_init();