From 0d0ebb6be9f0c87ea557c78c58dc8e06afe51183 Mon Sep 17 00:00:00 2001 From: Mario Scheithauer Date: Tue, 6 Nov 2018 10:35:57 +0100 Subject: [PATCH] siemens/mc_apl3: Disable CLKREQ of PCIe root ports All PCIe root ports of this mainboard do not have an associated CLKREQ signal. Therefore the ports are marked with "CLKREQ_DISABLED". Change-Id: I59c1132c6d273ccefeb1be6243577e1ae5064ef4 Signed-off-by: Mario Scheithauer Reviewed-on: https://review.coreboot.org/29502 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh Reviewed-by: Paul Menzel --- .../siemens/mc_apl1/variants/mc_apl3/devicetree.cb | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb index f3e8a77143..13ac4b5578 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb @@ -7,10 +7,10 @@ chip soc/intel/apollolake register "sci_irq" = "SCIS_IRQ10" # Disable unused clkreq of PCIe root ports - register "pcie_rp_clkreq_pin[0]" = "3" # PCIe-PCI-Bridge - register "pcie_rp_clkreq_pin[1]" = "2" # FPGA - register "pcie_rp_clkreq_pin[2]" = "0" # MACPHY - register "pcie_rp_clkreq_pin[3]" = "1" # MACPHY + register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"