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util/inteltool: add 6th gen. mobile core u/y series 

This adds the 6th gen. mobile core u/y series.

Change-Id: I7d802452353afe568e3880765dcd340f0437b392
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39568
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Michael Niewöhner 2020-03-14 22:39:30 +01:00 committed by Patrick Georgi
parent 01b6b245f0
commit 0d1366dedc
2 changed files with 6 additions and 0 deletions
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4
util/inteltool/inteltool.c
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@ -130,6 +130,10 @@ static const struct {
"6th generation (Skylake-S family) Core Processor (Desktop)" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_E,
"6th generation (Skylake family) Core Processor Xeon E (Server)" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_U,
"6th generation (Skylake family) Core Processor (Mobile)" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_Y,
"6th generation (Skylake family) Core Processor (Mobile)" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL, "Bay Trail" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U,
"7th generation (Kaby Lake family) Core Processor (Mobile)" },

2
util/inteltool/inteltool.h
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@ -284,6 +284,8 @@ static inline uint32_t inl(unsigned port)
#define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U 0x0a04 /* Haswell-ULT */
#define PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U 0x1604 /* Broadwell-ULT */
#define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D2 0x190f /* Skylake (Desktop) */
#define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_U 0x1904 /* Skylake (Mobile) */
#define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_Y 0x190c /* Skylake (Mobile) */
#define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M 0x1910 /* Skylake (Mobile) */
#define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST 0x1918 /* Skylake (Workstation) */
#define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D 0x191f /* Skylake (Desktop) */