nb/intel/x4x: Adapt post JEDEC for DDR3

Change-Id: I708f98dc2f36af73bb5933d186b4984649e149a1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

src/northbridge/intel/x4x/raminit_ddr23.c

@@ -2109,10 +2109,21 @@ void do_raminit(struct sysinfo *s, int fast_boot)
 	// After JEDEC reset
 	MCHBAR8(0x40) = MCHBAR8(0x40) & ~0x2;
 	FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) {
-		if (s->selected_timings.mem_clk == MEM_CLOCK_667MHz)
+		reg32 = (2 << 18);
-			reg32 = (2 << 18) | (3 << 13) | (5 << 8);
+		reg32 |= post_jedec_tab[s->selected_timings.fsb_clk]
-		else
+			[s->selected_timings.mem_clk - MEM_CLOCK_667MHz][0]
-			reg32 = (2 << 18) | (3 << 13) | (4 << 8);
+			<< 13;
+		if (s->selected_timings.mem_clk == MEM_CLOCK_667MHz &&
+			s->selected_timings.fsb_clk == FSB_CLOCK_1066MHz &&
+			ch == 1) {
+			reg32 |= (post_jedec_tab[s->selected_timings.fsb_clk]
+				[s->selected_timings.mem_clk - MEM_CLOCK_667MHz][1]
+				- 1) << 8;
+		} else {
+			reg32 |= post_jedec_tab[s->selected_timings.fsb_clk]
+				[s->selected_timings.mem_clk - MEM_CLOCK_667MHz][1]
+				<< 8;
+		}
 		MCHBAR32(0x400*ch + 0x274) = (MCHBAR32(0x400*ch + 0x274) & ~0xfff00) | reg32;
 		MCHBAR8(0x400*ch + 0x274) = MCHBAR8(0x400*ch + 0x274) & ~0x80;
 		MCHBAR8(0x400*ch + 0x26c) = MCHBAR8(0x400*ch + 0x26c) | 1;

src/northbridge/intel/x4x/raminit_tables.c

@@ -289,6 +289,23 @@ const u8 ddr3_emrs1_rtt_nom_config[16][4] = {  /* [Config][Rank] */
 	{0x81, 0x00, 0x81, 0x00},	/* 16S_16S */
 };
 
+const u8 post_jedec_tab[3][4][2]= /* [FSB][DDR freq][17:13 or 12:8] */
+{			/* FSB DDR */
+	{{0x3, 0x5}, /* 800 667 */
+	{0x3, 0x4}, /* 800 800 */
+	},
+	{{0x4, 0x8}, /* 1067 667 */
+	{0x4, 0x6}, /* 1067 800 */
+	{0x3, 0x5}, /* 1067 1066  */
+	},
+	{{0x5, 0x9}, /* 1333 667 */
+	{0x4, 0x7}, /* 1333 800 */
+	{0x4, 0x7}, /* 1333 1066 */
+	{0x4, 0x7} /* 1333 1333 */
+	},
+};
+
+
 const u32 ddr3_c2_tab[2][3][6][2] = { /* [n-mode][ddr3 freq][CAS][reg] */
 		/* 115h[15:0]	117h[23:0] */
 	{ /* 1N mode */

src/northbridge/intel/x4x/x4x.h

@@ -392,6 +392,7 @@ extern const struct dll_setting default_ddr3_800_dq[2][TOTAL_BYTELANES];
 extern const struct dll_setting default_ddr3_1067_dq[2][TOTAL_BYTELANES];
 extern const struct dll_setting default_ddr3_1333_dq[2][TOTAL_BYTELANES];
 extern const u8 ddr3_emrs1_rtt_nom_config[16][4];
+extern const u8 post_jedec_tab[3][4][2];
 extern const u32 ddr3_c2_tab[2][3][6][2];
 extern const u8 ddr3_c2_x264[3][6];
 extern const u16 ddr3_c2_x23c[3][6];