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mb/purism_librem_mini: Add child device, slot descriptions to PCIe RPs

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Change-Id: Id306100fc691dcbde48b65092d0be9d7e73c0722
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47189
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Matt DeVillier 2020-11-03 13:27:43 -06:00 committed by Michael Niewöhner
parent b808e7678d
commit 0d29bb72a1
1 changed files with 10 additions and 3 deletions
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13
src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb
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@ -204,22 +204,29 @@ chip soc/intel/cannonlake
device pci 1c.4 off end # PCI Express Port 5
device pci 1c.5 off end # PCI Express Port 6
device pci 1c.6 off end # PCI Express Port 7
device pci 1c.7 on # PCI Express Port 8 (WLAN)
device pci 1c.7 on # PCI Express Port 8
chip drivers/wifi/generic
device pci 00.0 on end # x1 M.2/E 2230 (WLAN)
end
register "PcieRpSlotImplemented[7]" = "1"
register "PcieRpEnable[7]" = "1"
register "PcieRpLtrEnable[7]" = "1"
smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther"
end
device pci 1d.0 off end # PCI Express Port 9
device pci 1d.1 on # PCI Express Port 10 (LAN)
device pci 1d.1 on # PCI Express Port 10
device pci 00.0 on end # x1 (LAN)
register "PcieRpSlotImplemented[9]" = "1"
register "PcieRpEnable[9]" = "1"
end
device pci 1d.2 off end # PCI Express Port 11
device pci 1d.3 off end # PCI Express Port 12
device pci 1d.4 on # PCI Express Port 13 (NVMe)
device pci 1d.4 on # PCI Express Port 13
device pci 00.0 on end # x4 M.2/M 2280 (NVMe)
register "PcieRpSlotImplemented[12]" = "1"
register "PcieRpEnable[12]" = "1"
register "PcieRpLtrEnable[12]" = "1"
smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X"
end
device pci 1d.5 off end # PCI Express Port 14
device pci 1d.6 off end # PCI Express Port 15