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amd/amdmct/mct_ddr3: Set prefetch double stride to improve performance 

Change-Id: I34ad85388c6b71f0d44bee13afd663e0b84545cd
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12037
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Timothy Pearson 2015-08-08 20:29:55 -05:00 committed by Stefan Reinauer
parent eb295a3e69
commit 0d2fdeb36a
1 changed files with 1 additions and 0 deletions
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src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
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@ -5313,6 +5313,7 @@ static void mct_FinalMCT_D(struct MCTStatStruc *pMCTstat,
val &= ~(0x7 << 8); /* CohPrefPrbLmt = 0x1 */ val &= ~(0x7 << 8); /* CohPrefPrbLmt = 0x1 */
val |= (0x1 << 8); val |= (0x1 << 8);
val |= (0x1 << 12); /* EnSplitDctLimits = 0x1 */ val |= (0x1 << 12); /* EnSplitDctLimits = 0x1 */
val |= (0x1 << 20); /* DblPrefEn = 0x1 */
val |= (0x7 << 22); /* PrefFourConf = 0x7 */ val |= (0x7 << 22); /* PrefFourConf = 0x7 */
val |= (0x7 << 25); /* PrefFiveConf = 0x7 */ val |= (0x7 << 25); /* PrefFiveConf = 0x7 */
val &= ~(0xf << 28); /* DcqBwThrotWm = 0x0 */ val &= ~(0xf << 28); /* DcqBwThrotWm = 0x0 */