Move DCACHE support into the cpu family for AMD model_fxx.
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4610 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
parent
e6804955c4
commit
0d5ced0e23
|
@ -1,15 +1,40 @@
|
|||
config HAVE_INIT_TIMER
|
||||
bool
|
||||
default y
|
||||
depends on CPU_AMD_SOCKET_F
|
||||
depends on CPU_AMD_MODEL_FXX
|
||||
|
||||
config HAVE_MOVNTI
|
||||
bool
|
||||
default y
|
||||
depends on CPU_AMD_SOCKET_F
|
||||
depends on CPU_AMD_MODEL_FXX
|
||||
|
||||
config CPU_ADDR_BITS
|
||||
int
|
||||
default 40
|
||||
depends on CPU_AMD_SOCKET_F
|
||||
depends on CPU_AMD_MODEL_FXX
|
||||
|
||||
config USE_PRINTK_IN_CAR
|
||||
bool
|
||||
default y
|
||||
depends on CPU_AMD_MODEL_FXX
|
||||
|
||||
config USE_DCACHE_RAM
|
||||
bool
|
||||
default y
|
||||
depends on CPU_AMD_MODEL_FXX
|
||||
|
||||
config DCACHE_RAM_BASE
|
||||
hex
|
||||
default 0xc8000
|
||||
depends on CPU_AMD_MODEL_FXX
|
||||
|
||||
config DCACHE_RAM_SIZE
|
||||
hex
|
||||
default 0x08000
|
||||
depends on CPU_AMD_MODEL_FXX
|
||||
|
||||
config DCACHE_RAM_GLOBAL_VAR_SIZE
|
||||
hex
|
||||
default 0x01000
|
||||
depends on CPU_AMD_MODEL_FXX
|
||||
|
||||
|
|
|
@ -12,3 +12,8 @@ config K8_HT_FREQ_1G_SUPPORT
|
|||
hex
|
||||
default 1
|
||||
depends on CPU_AMD_SOCKET_940
|
||||
|
||||
config CPU_AMD_MODEL_FXX
|
||||
bool
|
||||
default y
|
||||
depends on CPU_AMD_SOCKET_940
|
||||
|
|
Loading…
Reference in New Issue