soc/intel/meteorlake: Choose coreboot doing MP Init over FSP

This patch enables coreboot doing Multiprocessor Initialization (MP)
for Meteor Lake CPU using the native coreboot drivers and passes the
MP PPI data structure to let FSP to perform CPU feature programming
(anything that is restricted) as part of FSP-S.

Additionally, modify the kconfig inclusion order alphabetically.

BUG=b:219061518, b:219053812
TEST=Able to bring all APs from reset by coreboot and successfully
able to perform all CPU feature programming using MP PPI services.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ic2781ee0b39e42aa579b72d3d4ee6586d5a89a02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65742
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/meteorlake/Kconfig

@@ -28,18 +28,18 @@ config CPU_SPECIFIC_OPTIONS
 	select GENERIC_GPIO_LIB
 	select HAVE_DEBUG_RAM_SETUP
 	select HAVE_FSP_GOP
-	select INTEL_DESCRIPTOR_MODE_CAPABLE
 	select HAVE_SMI_HANDLER
 	select IDT_IN_EVERY_STAGE
 	select INTEL_CAR_NEM
+	select INTEL_DESCRIPTOR_MODE_CAPABLE
 	select INTEL_GMA_ACPI
 	select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
-	select IOAPIC
 	select INTEL_TME
-	select USE_INTEL_FSP_MP_INIT
-	select MRC_SETTINGS_PROTECT
-	select PARALLEL_MP_AP_WORK
+	select IOAPIC
 	select MICROCODE_BLOB_UNDISCLOSED
+	select MRC_SETTINGS_PROTECT
+	select MP_SERVICES_PPI_V2
+	select PARALLEL_MP_AP_WORK
 	select PLATFORM_USES_FSP2_3
 	select PMC_GLOBAL_RESET_ENABLE_LOCK
 	select SOC_INTEL_COMMON
@@ -88,7 +88,6 @@ config CPU_SPECIFIC_OPTIONS
 	select TSC_MONOTONIC_TIMER
 	select UDELAY_TSC
 	select UDK_202111_BINDING
-	select DISPLAY_FSP_VERSION_INFO
 
 config MAX_CPUS
 	int