soc/intel/broadwell: Align ACPI with Haswell/Lynxpoint
Drop unnecessary smbus.asl in favor of southbridge common code. Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 does not change. Change-Id: I13b35d2155a2cede0a56846b8bf8a79d4ebfc7b3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46757 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Angel Pons
parent
f239b5a9f3
commit
0d8924d880
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@ -9,8 +9,7 @@ Scope (\_SB.PCI0.MCHC)
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Name (CTCU, 2) /* CTDP Up Select */
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Name (SPL1, 0) /* Saved PL1 value */
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OperationRegion (MCHB, SystemMemory,
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Add (MCH_BASE_ADDRESS, 0x5000), 0x1000)
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OperationRegion (MCHB, SystemMemory, MCH_BASE_ADDRESS + 0x5000, 0x1000)
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Field (MCHB, DWordAcc, Lock, Preserve)
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{
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Offset (0x930), /* PACKAGE_POWER_SKU */
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@ -62,17 +61,16 @@ Scope (\_SB.PCI0.MCHC)
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External (\_SB.CP00._PSS)
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Method (PSSS, 1, NotSerialized)
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{
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Store (One, Local0) /* Start at P1 */
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Store (SizeOf (\_SB.CP00._PSS), Local1)
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Local0 = 1 /* Start at P1 */
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Local1 = SizeOf (\_SB.CP00._PSS)
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While (LLess (Local0, Local1)) {
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While (Local0 < Local1) {
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/* Store _PSS entry Control value to Local2 */
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ShiftRight (DeRefOf (Index (DeRefOf (Index
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(\_SB.CP00._PSS, Local0)), 4)), 8, Local2)
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If (LEqual (Local2, Arg0)) {
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Return (Subtract (Local0, 1))
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Local2 = DeRefOf (Index (DeRefOf (Index (\_SB.CP00._PSS, Local0)), 4)) >> 8
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If (Local2 == Arg0) {
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Return (Local0 - 1)
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}
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Increment (Local0)
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Local0++
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}
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Return (0)
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@ -83,7 +81,7 @@ Scope (\_SB.PCI0.MCHC)
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{
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/* Haswell ULT PL2 = 25W */
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/* FIXME: update for broadwell */
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Return (Multiply (25, 8))
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Return (25 * 8)
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}
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/* Set Config TDP Down */
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@ -92,31 +90,31 @@ Scope (\_SB.PCI0.MCHC)
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If (Acquire (CTCM, 100)) {
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Return (0)
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}
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If (LEqual (CTCD, CTCC)) {
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If (CTCD == CTCC) {
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Release (CTCM)
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Return (0)
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}
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Store ("Set TDP Down", Debug)
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Debug = "Set TDP Down"
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/* Set CTC */
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Store (CTCD, CTCS)
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CTCS = CTCD
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/* Set TAR */
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Store (TARD, TARS)
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TARS = TARD
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/* Set PPC limit and notify OS */
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Store (PSSS (TARD), PPCM)
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PPCM = PSSS (TARD)
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PPCN ()
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/* Set PL2 */
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Store (CPL2 (CTDD), PL2V)
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PL2V = CPL2 (CTDD)
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/* Set PL1 */
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Store (CTDD, PL1V)
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PL1V = CTDD
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/* Store the new TDP Down setting */
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Store (CTCD, CTCC)
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CTCC = CTCD
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Release (CTCM)
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Return (1)
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@ -128,31 +126,31 @@ Scope (\_SB.PCI0.MCHC)
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If (Acquire (CTCM, 100)) {
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Return (0)
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}
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If (LEqual (CTCN, CTCC)) {
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If (CTCN == CTCC) {
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Release (CTCM)
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Return (0)
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}
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Store ("Set TDP Nominal", Debug)
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Debug = "Set TDP Nominal"
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/* Set PL1 */
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Store (CTDN, PL1V)
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PL1V = CTDN
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/* Set PL2 */
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Store (CPL2 (CTDN), PL2V)
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PL2V = CPL2 (CTDN)
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/* Set PPC limit and notify OS */
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Store (PSSS (TARN), PPCM)
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PPCM = PSSS (TARN)
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PPCN ()
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/* Set TAR */
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Store (TARN, TARS)
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TARS = TARN
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/* Set CTC */
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Store (CTCN, CTCS)
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CTCS = CTCN
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/* Store the new TDP Nominal setting */
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Store (CTCN, CTCC)
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CTCC = CTCN
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Release (CTCM)
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Return (1)
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@ -161,7 +159,7 @@ Scope (\_SB.PCI0.MCHC)
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/* Calculate PL1 value based on requested TDP */
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Method (TDPP, 1, NotSerialized)
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{
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Return (Multiply (ShiftLeft (Subtract (PUNI, 1), 2), Arg0))
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Return (((PUNI - 1) << 2) * Arg0)
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}
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/* Enable Controllable TDP to limit PL1 to requested value */
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@ -171,22 +169,22 @@ Scope (\_SB.PCI0.MCHC)
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Return (0)
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}
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Store ("Enable PL1 Limit", Debug)
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Debug = "Enable PL1 Limit"
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/* Set _PPC to LFM */
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Store (PSSS (LFM_), Local0)
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Add (Local0, 1, PPCM)
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Local0 = PSSS (LFM_)
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PPCM = Local0 + 1
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\PPCN ()
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/* Set TAR to LFM-1 */
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Subtract (LFM_, 1, TARS)
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TARS = LFM_ - 1
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/* Set PL1 to desired value */
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Store (PL1V, SPL1)
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Store (TDPP (Arg0), PL1V)
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SPL1 = PL1V
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PL1V = TDPP (Arg0)
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/* Set PL1 CLAMP bit */
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Store (One, PL1C)
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PL1C = 1
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Release (CTCM)
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Return (1)
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@ -199,19 +197,19 @@ Scope (\_SB.PCI0.MCHC)
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Return (0)
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}
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Store ("Disable PL1 Limit", Debug)
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Debug = "Disable PL1 Limit"
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/* Clear PL1 CLAMP bit */
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Store (Zero, PL1C)
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PL1C = 0
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/* Set PL1 to normal value */
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Store (SPL1, PL1V)
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PL1V = SPL1
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/* Set TAR to 0 */
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Store (Zero, TARS)
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TARS = 0
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/* Set _PPC to 0 */
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Store (Zero, PPCM)
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PPCM = 0
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\PPCN ()
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Release (CTCM)
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@ -181,6 +181,6 @@ Device (LPCB)
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#include "gpio.asl"
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#include "irqlinks.asl"
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#include <acpi/ec.asl>
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#include <acpi/superio.asl>
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#include "acpi/ec.asl"
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#include "acpi/superio.asl"
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}
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@ -60,7 +60,7 @@ Scope (\)
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#include "sata.asl"
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// SMBus 0:1f.3
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#include "smbus.asl"
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#include <southbridge/intel/common/acpi/smbus.asl>
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// Serial IO
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#include "serialio.asl"
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@ -1,8 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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// Intel SMBus Controller 0:1f.3
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Device (SBUS)
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{
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Name (_ADR, 0x001f0003)
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}
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