rockchip: gru: update the hynix lpddr3 config to run at 928MHz

Update the DDR config and DRAM driver to allow running at up to
928MHz. Kevin config/clock rate are not being changed, but Gru now
runs at 928 MHz.

BRANCH=none
BUG=chrome-os-partner:51537
TEST=booted Kevin and Gru to Linux prompt. Ran stressapptest for 10 min on Gru,

Change-Id: I66c1a171d5c7d05b2878c7bc5eaa0d436c7a1be2
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 8baf0d82816a7ea1c4428e15caeefa2795d001f9
Original-Change-Id: I5e1d6d1025f10203da8f11afc3bbdf95f133c586
Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/343984
Original-Reviewed-by: Stephen Barber <smbarber@chromium.org>
Reviewed-on: https://review.coreboot.org/15027
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>

src/mainboard/google/gru/sdram_configs.c

@@ -22,7 +22,13 @@
 #include <types.h>
 
 static struct rk3399_sdram_params sdram_configs[] = {
-#include "sdram_inf/sdram-lpddr3-hynix-4GB.inc"
+#if IS_ENABLED(CONFIG_BOARD_GOOGLE_GRU)
+#include "sdram_inf/gru-sdram-lpddr3-hynix-4GB.inc"
+#elif IS_ENABLED(CONFIG_BOARD_GOOGLE_KEVIN)
+#include "sdram_inf/kevin-sdram-lpddr3-hynix-4GB.inc"
+#else
+#error "What is your board name?"
+#endif
 };
 
 const struct rk3399_sdram_params *get_sdram_config()

src/mainboard/google/gru/sdram_inf/kevin-sdram-lpddr3-hynix-4GB.inc

@@ -1,3 +1,15 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
 {
 	{
 		{

src/soc/rockchip/rk3399/clock.c

@@ -549,6 +549,10 @@ void rkclk_configure_ddr(unsigned int hz)
 		dpll_cfg = (struct pll_div)
 		{.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1};
 		break;
+	case 928*MHz:
+		dpll_cfg = (struct pll_div)
+		{.refdiv = 1, .fbdiv = 116, .postdiv1 = 3, .postdiv2 = 1};
+		break;
 	default:
 		die("Unsupported SDRAM frequency, add to clock.c!");
 	}

src/soc/rockchip/rk3399/sdram.c

@@ -819,7 +819,7 @@ void sdram_init(const struct rk3399_sdram_params *sdram_params)
 	if ((sdram_params->dramtype == DDR3
 			&& sdram_params->ddr_freq > 800*MHz) ||
 	    (sdram_params->dramtype == LPDDR3
-			&& sdram_params->ddr_freq > 800*MHz) ||
+			&& sdram_params->ddr_freq > 928*MHz) ||
 	    (sdram_params->dramtype == LPDDR4
 			&& sdram_params->ddr_freq > 800*MHz))
 		die("SDRAM frequency is to high!");