vendorcode/amd/pi/00670F00/Proc/Psp: Remove VENDORCODE_FULL_SUPPORT

Remove VENDORCODE_FULL_SUPPORT from file:
vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspBaseLib.c

BUG=b:112578491
TEST=none, VENDORCODE_FULL_SUPPORT already not used.

Change-Id: I0d590b175a3cf0426580dc9ee5164b3cedc838e2
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28089
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Richard Spiegel 2018-08-14 08:26:02 -07:00 committed by Martin Roth
parent 01b6ea4126
commit 0d9b441385
1 changed files with 0 additions and 375 deletions

View File

@ -223,115 +223,6 @@ GetPspDirBase (
return (FALSE);
}
#if IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT)
/**
* Get specific PSP Entry information, this routine will auto detect the processor for loading
* correct PSP Directory
*
*
*
* @param[in] EntryType PSP DIR Entry Type
* @param[in,out] EntryAddress Address of the specific PSP Entry
* @param[in,out] EntrySize Size of the specific PSP Entry
*/
BOOLEAN
PSPEntryInfo (
IN PSP_DIRECTORY_ENTRY_TYPE EntryType,
IN OUT UINT64 *EntryAddress,
IN OUT UINT32 *EntrySize
)
{
PSP_DIRECTORY *PspDir;
UINTN i;
PROGRAM_ID ProgramId;
PspDir = NULL;
if (GetPspDirBase ((UINT32 *)&PspDir ) != TRUE) {
return FALSE;
}
ProgramId = PspGetProgarmId ();
//Append BR Program ID
if ((ProgramId == BR_PROGRAM) &&
((EntryType == SMU_OFFCHIP_FW) ||
(EntryType == SMU_OFF_CHIP_FW_2) ||
(EntryType == AMD_SCS_BINARY))) {
EntryType |= (PSP_ENTRY_BR_PROGRAM_ID << 8);
}
for (i = 0; i < PspDir->Header.TotalEntries; i++) {
if (PspDir->PspEntry[i].Type == EntryType) {
*EntryAddress = PspDir->PspEntry[i].Location;
*EntrySize = PspDir->PspEntry[i].Size;
return (TRUE);
}
}
return (FALSE);
}
BOOLEAN
PspSoftWareFuseInfo (
IN OUT UINTN *FuseSpiAddress,
IN OUT UINT64 *FuseValue
)
{
PSP_DIRECTORY *PspDir;
UINTN i;
PspDir = NULL;
if (GetPspDirBase ((UINT32 *)&PspDir ) != TRUE) {
return FALSE;
}
for (i = 0; i < PspDir->Header.TotalEntries; i++) {
if (PspDir->PspEntry[i].Type == AMD_SOFT_FUSE_CHAIN_01) {
*FuseSpiAddress = (UINT32) (UINTN) &PspDir->PspEntry[i].Location;
*FuseValue = PspDir->PspEntry[i].Location;
return (TRUE);
}
}
return (FALSE);
}
static UINT32 Fletcher32 (
IN OUT UINT16 *data,
IN UINTN words
)
{
UINT32 sum1;
UINT32 sum2;
UINTN tlen;
sum1 = 0xffff;
sum2 = 0xffff;
while (words) {
tlen = words >= 359 ? 359 : words;
words -= tlen;
do {
sum2 += sum1 += *data++;
} while (--tlen);
sum1 = (sum1 & 0xffff) + (sum1 >> 16);
sum2 = (sum2 & 0xffff) + (sum2 >> 16);
}
// Second reduction step to reduce sums to 16 bits
sum1 = (sum1 & 0xffff) + (sum1 >> 16);
sum2 = (sum2 & 0xffff) + (sum2 >> 16);
return sum2 << 16 | sum1;
}
VOID
UpdataPspDirCheckSum (
IN OUT PSP_DIRECTORY *PspDir
)
{
PspDir->Header.Checksum = Fletcher32 ((UINT16 *) &PspDir->Header.TotalEntries, \
(sizeof (PSP_DIRECTORY_HEADER) - OFFSET_OF (PSP_DIRECTORY_HEADER, TotalEntries) + PspDir->Header.TotalEntries * sizeof (PSP_DIRECTORY_ENTRY)) / 2);
}
#endif /* IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT) */
/**
Check if PSP device is present
@ -353,76 +244,6 @@ CheckPspDevicePresent (
return (FALSE);
}
#if IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT)
/**
Check PSP Platform Seucre Enable State
HVB & Secure S3 (Resume vector set to Dram, & core content will restore by uCode)
will be applied if Psp Plaform Secure is enabled
@retval BOOLEAN 0: PSP Platform Secure Disabled, 1: PSP Platform Secure Enabled
**/
BOOLEAN
CheckPspPlatformSecureEnable (
VOID
)
{
UINT32 SecureFuseReg;
PspLibPciWriteConfig ( (UINT32)PCI_CONFIG_SMU_INDIRECT_INDEX, (UINT32)SMU_CC_PSP_FUSES_STATUS);
SecureFuseReg = PspLibPciReadConfig ( (UINT32)PCI_CONFIG_SMU_INDIRECT_DATA);
if (SecureFuseReg &= PLATFORM_SECURE_BOOT_EN) {
return (TRUE);
}
return (FALSE);
}
/**
Check PSP Recovery Flag
Target will set Recovery flag if some PSP entry point by PSP directory has been corrupted.
@retval BOOLEAN 0: Recovery Flag is cleared, 1: Recovery Flag has been set
**/
BOOLEAN
CheckPspRecoveryFlag (
VOID
)
{
MBOX_STATUS *MboxStatus;
//Init PSP MMIO
PspBarInitEarly ();
GetPspMboxStatus (&MboxStatus);
return (BOOLEAN) (MboxStatus->Recovery);
}
/**
Return the PspMbox MMIO location
@retval BOOLEAN FALSE: ERROR, TRUE: SUCCEED
**/
BOOLEAN
GetPspMboxStatus (
IN OUT MBOX_STATUS **MboxStatus
)
{
UINT32 PspMmio;
if (GetPspBar3Addr (&PspMmio) == FALSE) {
return (FALSE);
}
*MboxStatus = (MBOX_STATUS *)( (UINTN)PspMmio + PSP_MAILBOX_BASE + PSP_MAILBOX_STATUS_OFFSET); // PSPMbox base is at offset CP2MSG_28 ie. offset 28*4 = 0x70
return (TRUE);
}
#endif /* IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT) */
BOOLEAN
PspBarInitEarly ()
{
@ -458,33 +279,6 @@ PspBarInitEarly ()
return (TRUE);
}
#if IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT)
/**
Return the PspMMIO MMIO location
@param[in] PspMmio Pointer to Psp MMIO address
@retval BOOLEAN 0: Error, 1 Success
**/
BOOLEAN
GetPspBar1Addr (
IN OUT UINT32 *PspMmio
)
{
if (CheckPspDevicePresent () == FALSE) {
return (FALSE);
}
*PspMmio = PspLibPciReadPspConfig (PSP_PCI_BAR1_REG);
if ((*PspMmio) == 0xffffffff) {
return (FALSE);
}
return (TRUE);
}
#endif /* IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT) */
/**
Return the PspMMIO MMIO location
@ -519,172 +313,3 @@ GetPspBar3Addr (
return (TRUE);
}
#if IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT)
/**
* Acquire the Mutex for access PSP,X86 co-accessed register
* Call this routine before access SMIx98 & SMIxA8
*
*/
VOID
AcquirePspSmiRegMutex (
VOID
)
{
UINT32 PspBarAddr;
UINT32 MutexReg0;
UINT32 MutexReg1;
PspBarAddr = 0;
if (GetPspBar3Addr (&PspBarAddr)) {
MutexReg0 = PspBarAddr + PSP_MUTEX_REG0_OFFSET;
MutexReg1 = PspBarAddr + PSP_MUTEX_REG1_OFFSET;
*(volatile UINT32*)(UINTN)(MutexReg0) |= BIT0;
*(volatile UINT32*)(UINTN)(MutexReg1) |= BIT0;
//Wait till PSP FW release the mutex
while ((*(volatile UINT32*)(UINTN)(MutexReg0)& BIT1) && (*(volatile UINT32*)(UINTN)(MutexReg1) & BIT0)) {
;
}
}
}
/**
* Release the Mutex for access PSP,X86 co-accessed register
* Call this routine after access SMIx98 & SMIxA8
*
*/
VOID
ReleasePspSmiRegMutex (
VOID
)
{
UINT32 PspBarAddr;
UINT32 MutexReg0;
PspBarAddr = 0;
if (GetPspBar3Addr (&PspBarAddr)) {
MutexReg0 = PspBarAddr + PSP_MUTEX_REG0_OFFSET;
*(volatile UINT32*)(UINTN)(MutexReg0) &= ~BIT0;
}
}
/*---------------------------------------------------------------------------------------*/
/**
* Returns the access width mask for the processor
*
*
* @param[in] AccessWidth Access width
* @retval Width in number of bytes
*/
UINT8
static PspLibAccessWidth (
IN ACCESS_WIDTH AccessWidth
)
{
UINT8 Width;
switch (AccessWidth) {
case AccessWidth8:
case AccessS3SaveWidth8:
Width = 1;
break;
case AccessWidth16:
case AccessS3SaveWidth16:
Width = 2;
break;
case AccessWidth32:
case AccessS3SaveWidth32:
Width = 4;
break;
case AccessWidth64:
case AccessS3SaveWidth64:
Width = 8;
break;
default:
Width = 0;
}
return Width;
}
/*----------------------------------------------------------------------------------------*/
/**
* Read GNB indirect registers
*
*
*
* @param[in] Address PCI address of indirect register
* @param[in] IndirectAddress Offset of indirect register
* @param[in] Width Width
* @param[out] Value Pointer to value
*/
VOID
PspLibPciIndirectRead (
IN PCI_ADDR Address,
IN UINT32 IndirectAddress,
IN ACCESS_WIDTH Width,
OUT VOID *Value
)
{
UINT32 IndexOffset;
IndexOffset = PspLibAccessWidth (Width);
LibAmdPciWrite (Width, Address, &IndirectAddress, NULL);
Address.AddressValue += IndexOffset;
LibAmdPciRead (Width, Address, Value, NULL);
}
/*----------------------------------------------------------------------------------------*/
/**
* Write GNB indirect registers
*
*
*
* @param[in] Address PCI address of indirect register
* @param[in] IndirectAddress Offset of indirect register
* @param[in] Width Width
* @param[in] Value Pointer to value
*/
VOID
PspLibPciIndirectWrite (
IN PCI_ADDR Address,
IN UINT32 IndirectAddress,
IN ACCESS_WIDTH Width,
IN VOID *Value
)
{
UINT32 IndexOffset;
IndexOffset = PspLibAccessWidth (Width);
LibAmdPciWrite (Width, Address, &IndirectAddress, NULL);
Address.AddressValue += IndexOffset;
LibAmdPciWrite (Width, Address, Value, NULL);
}
BOOLEAN
IsS3Resume (
)
{
UINT16 AcpiPm1CntBlk;
UINT16 SleepType;
UINT8 PmioAddr;
AcpiPm1CntBlk = 0;
//Get AcpiPm1CntBlk address
//PMIO register can only allow 8bits access
PmioAddr = PMIO_REG62;
LibAmdIoWrite (AccessWidth8, PMIO_INDEX_PORT, &PmioAddr, NULL);
LibAmdIoRead (AccessWidth8, PMIO_DATA_PORT, &AcpiPm1CntBlk, NULL);
PmioAddr++;
LibAmdIoWrite (AccessWidth8, PMIO_INDEX_PORT, &PmioAddr, NULL);
LibAmdIoRead (AccessWidth8, PMIO_DATA_PORT, ((UINT8 *) &AcpiPm1CntBlk) + 1, NULL);
//Get Sleep type
LibAmdIoRead (AccessWidth16, AcpiPm1CntBlk, &SleepType, NULL);
SleepType = SleepType & 0x1C00;
SleepType = ((SleepType >> 10) & 7);
return ((SleepType == 3) ? TRUE : FALSE);
}
#endif /* IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT) */