vendorcode/amd/pi/00670F00/Proc/Psp: Remove VENDORCODE_FULL_SUPPORT
Remove VENDORCODE_FULL_SUPPORT from file: vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspBaseLib.c BUG=b:112578491 TEST=none, VENDORCODE_FULL_SUPPORT already not used. Change-Id: I0d590b175a3cf0426580dc9ee5164b3cedc838e2 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28089 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Richard Spiegel
Martin Roth
parent
01b6ea4126
commit
0d9b441385
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@ -223,115 +223,6 @@ GetPspDirBase (
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return (FALSE);
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}
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#if IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT)
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/**
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* Get specific PSP Entry information, this routine will auto detect the processor for loading
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* correct PSP Directory
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*
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*
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*
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* @param[in] EntryType PSP DIR Entry Type
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* @param[in,out] EntryAddress Address of the specific PSP Entry
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* @param[in,out] EntrySize Size of the specific PSP Entry
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*/
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BOOLEAN
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PSPEntryInfo (
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IN PSP_DIRECTORY_ENTRY_TYPE EntryType,
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IN OUT UINT64 *EntryAddress,
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IN OUT UINT32 *EntrySize
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)
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{
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PSP_DIRECTORY *PspDir;
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UINTN i;
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PROGRAM_ID ProgramId;
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PspDir = NULL;
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if (GetPspDirBase ((UINT32 *)&PspDir ) != TRUE) {
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return FALSE;
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}
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ProgramId = PspGetProgarmId ();
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//Append BR Program ID
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if ((ProgramId == BR_PROGRAM) &&
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((EntryType == SMU_OFFCHIP_FW) ||
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(EntryType == SMU_OFF_CHIP_FW_2) ||
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(EntryType == AMD_SCS_BINARY))) {
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EntryType |= (PSP_ENTRY_BR_PROGRAM_ID << 8);
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}
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for (i = 0; i < PspDir->Header.TotalEntries; i++) {
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if (PspDir->PspEntry[i].Type == EntryType) {
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*EntryAddress = PspDir->PspEntry[i].Location;
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*EntrySize = PspDir->PspEntry[i].Size;
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return (TRUE);
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}
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}
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return (FALSE);
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}
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BOOLEAN
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PspSoftWareFuseInfo (
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IN OUT UINTN *FuseSpiAddress,
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IN OUT UINT64 *FuseValue
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)
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{
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PSP_DIRECTORY *PspDir;
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UINTN i;
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PspDir = NULL;
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if (GetPspDirBase ((UINT32 *)&PspDir ) != TRUE) {
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return FALSE;
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}
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for (i = 0; i < PspDir->Header.TotalEntries; i++) {
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if (PspDir->PspEntry[i].Type == AMD_SOFT_FUSE_CHAIN_01) {
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*FuseSpiAddress = (UINT32) (UINTN) &PspDir->PspEntry[i].Location;
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*FuseValue = PspDir->PspEntry[i].Location;
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return (TRUE);
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}
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}
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return (FALSE);
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}
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static UINT32 Fletcher32 (
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IN OUT UINT16 *data,
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IN UINTN words
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)
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{
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UINT32 sum1;
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UINT32 sum2;
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UINTN tlen;
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sum1 = 0xffff;
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sum2 = 0xffff;
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while (words) {
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tlen = words >= 359 ? 359 : words;
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words -= tlen;
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do {
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sum2 += sum1 += *data++;
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} while (--tlen);
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sum1 = (sum1 & 0xffff) + (sum1 >> 16);
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sum2 = (sum2 & 0xffff) + (sum2 >> 16);
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}
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// Second reduction step to reduce sums to 16 bits
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sum1 = (sum1 & 0xffff) + (sum1 >> 16);
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sum2 = (sum2 & 0xffff) + (sum2 >> 16);
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return sum2 << 16 | sum1;
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}
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VOID
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UpdataPspDirCheckSum (
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IN OUT PSP_DIRECTORY *PspDir
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)
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{
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PspDir->Header.Checksum = Fletcher32 ((UINT16 *) &PspDir->Header.TotalEntries, \
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(sizeof (PSP_DIRECTORY_HEADER) - OFFSET_OF (PSP_DIRECTORY_HEADER, TotalEntries) + PspDir->Header.TotalEntries * sizeof (PSP_DIRECTORY_ENTRY)) / 2);
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}
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#endif /* IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT) */
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/**
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Check if PSP device is present
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@ -353,76 +244,6 @@ CheckPspDevicePresent (
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return (FALSE);
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}
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#if IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT)
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/**
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Check PSP Platform Seucre Enable State
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HVB & Secure S3 (Resume vector set to Dram, & core content will restore by uCode)
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will be applied if Psp Plaform Secure is enabled
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@retval BOOLEAN 0: PSP Platform Secure Disabled, 1: PSP Platform Secure Enabled
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**/
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BOOLEAN
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CheckPspPlatformSecureEnable (
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VOID
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)
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{
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UINT32 SecureFuseReg;
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PspLibPciWriteConfig ( (UINT32)PCI_CONFIG_SMU_INDIRECT_INDEX, (UINT32)SMU_CC_PSP_FUSES_STATUS);
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SecureFuseReg = PspLibPciReadConfig ( (UINT32)PCI_CONFIG_SMU_INDIRECT_DATA);
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if (SecureFuseReg &= PLATFORM_SECURE_BOOT_EN) {
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return (TRUE);
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}
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return (FALSE);
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}
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/**
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Check PSP Recovery Flag
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Target will set Recovery flag if some PSP entry point by PSP directory has been corrupted.
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@retval BOOLEAN 0: Recovery Flag is cleared, 1: Recovery Flag has been set
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**/
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BOOLEAN
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CheckPspRecoveryFlag (
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VOID
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)
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{
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MBOX_STATUS *MboxStatus;
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//Init PSP MMIO
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PspBarInitEarly ();
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GetPspMboxStatus (&MboxStatus);
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return (BOOLEAN) (MboxStatus->Recovery);
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}
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/**
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Return the PspMbox MMIO location
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@retval BOOLEAN FALSE: ERROR, TRUE: SUCCEED
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**/
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BOOLEAN
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GetPspMboxStatus (
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IN OUT MBOX_STATUS **MboxStatus
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)
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{
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UINT32 PspMmio;
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if (GetPspBar3Addr (&PspMmio) == FALSE) {
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return (FALSE);
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}
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*MboxStatus = (MBOX_STATUS *)( (UINTN)PspMmio + PSP_MAILBOX_BASE + PSP_MAILBOX_STATUS_OFFSET); // PSPMbox base is at offset CP2MSG_28 ie. offset 28*4 = 0x70
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return (TRUE);
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}
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#endif /* IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT) */
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BOOLEAN
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PspBarInitEarly ()
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{
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@ -458,33 +279,6 @@ PspBarInitEarly ()
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return (TRUE);
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}
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#if IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT)
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/**
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Return the PspMMIO MMIO location
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@param[in] PspMmio Pointer to Psp MMIO address
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@retval BOOLEAN 0: Error, 1 Success
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**/
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BOOLEAN
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GetPspBar1Addr (
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IN OUT UINT32 *PspMmio
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)
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{
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if (CheckPspDevicePresent () == FALSE) {
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return (FALSE);
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}
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*PspMmio = PspLibPciReadPspConfig (PSP_PCI_BAR1_REG);
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if ((*PspMmio) == 0xffffffff) {
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return (FALSE);
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}
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return (TRUE);
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}
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#endif /* IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT) */
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/**
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Return the PspMMIO MMIO location
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@ -519,172 +313,3 @@ GetPspBar3Addr (
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return (TRUE);
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}
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#if IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT)
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/**
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* Acquire the Mutex for access PSP,X86 co-accessed register
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* Call this routine before access SMIx98 & SMIxA8
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*
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*/
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VOID
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AcquirePspSmiRegMutex (
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VOID
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)
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{
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UINT32 PspBarAddr;
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UINT32 MutexReg0;
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UINT32 MutexReg1;
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PspBarAddr = 0;
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if (GetPspBar3Addr (&PspBarAddr)) {
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MutexReg0 = PspBarAddr + PSP_MUTEX_REG0_OFFSET;
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MutexReg1 = PspBarAddr + PSP_MUTEX_REG1_OFFSET;
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*(volatile UINT32*)(UINTN)(MutexReg0) |= BIT0;
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*(volatile UINT32*)(UINTN)(MutexReg1) |= BIT0;
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//Wait till PSP FW release the mutex
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while ((*(volatile UINT32*)(UINTN)(MutexReg0)& BIT1) && (*(volatile UINT32*)(UINTN)(MutexReg1) & BIT0)) {
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;
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}
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}
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}
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/**
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* Release the Mutex for access PSP,X86 co-accessed register
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* Call this routine after access SMIx98 & SMIxA8
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*
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*/
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VOID
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ReleasePspSmiRegMutex (
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VOID
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)
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{
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UINT32 PspBarAddr;
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UINT32 MutexReg0;
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PspBarAddr = 0;
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if (GetPspBar3Addr (&PspBarAddr)) {
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MutexReg0 = PspBarAddr + PSP_MUTEX_REG0_OFFSET;
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*(volatile UINT32*)(UINTN)(MutexReg0) &= ~BIT0;
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}
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}
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/*---------------------------------------------------------------------------------------*/
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/**
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* Returns the access width mask for the processor
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*
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*
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* @param[in] AccessWidth Access width
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* @retval Width in number of bytes
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*/
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UINT8
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static PspLibAccessWidth (
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IN ACCESS_WIDTH AccessWidth
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)
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{
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UINT8 Width;
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switch (AccessWidth) {
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case AccessWidth8:
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case AccessS3SaveWidth8:
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Width = 1;
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break;
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case AccessWidth16:
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case AccessS3SaveWidth16:
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Width = 2;
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break;
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case AccessWidth32:
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case AccessS3SaveWidth32:
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Width = 4;
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break;
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case AccessWidth64:
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case AccessS3SaveWidth64:
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Width = 8;
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break;
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default:
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Width = 0;
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}
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return Width;
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}
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/*----------------------------------------------------------------------------------------*/
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/**
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* Read GNB indirect registers
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*
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*
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*
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* @param[in] Address PCI address of indirect register
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* @param[in] IndirectAddress Offset of indirect register
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* @param[in] Width Width
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* @param[out] Value Pointer to value
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*/
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VOID
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PspLibPciIndirectRead (
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IN PCI_ADDR Address,
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IN UINT32 IndirectAddress,
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IN ACCESS_WIDTH Width,
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OUT VOID *Value
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)
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{
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UINT32 IndexOffset;
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IndexOffset = PspLibAccessWidth (Width);
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LibAmdPciWrite (Width, Address, &IndirectAddress, NULL);
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Address.AddressValue += IndexOffset;
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LibAmdPciRead (Width, Address, Value, NULL);
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}
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/*----------------------------------------------------------------------------------------*/
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/**
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* Write GNB indirect registers
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*
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*
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*
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* @param[in] Address PCI address of indirect register
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* @param[in] IndirectAddress Offset of indirect register
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* @param[in] Width Width
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* @param[in] Value Pointer to value
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*/
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VOID
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PspLibPciIndirectWrite (
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IN PCI_ADDR Address,
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IN UINT32 IndirectAddress,
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IN ACCESS_WIDTH Width,
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IN VOID *Value
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)
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{
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UINT32 IndexOffset;
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IndexOffset = PspLibAccessWidth (Width);
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LibAmdPciWrite (Width, Address, &IndirectAddress, NULL);
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Address.AddressValue += IndexOffset;
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LibAmdPciWrite (Width, Address, Value, NULL);
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}
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BOOLEAN
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IsS3Resume (
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)
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{
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UINT16 AcpiPm1CntBlk;
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UINT16 SleepType;
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UINT8 PmioAddr;
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AcpiPm1CntBlk = 0;
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//Get AcpiPm1CntBlk address
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//PMIO register can only allow 8bits access
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PmioAddr = PMIO_REG62;
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LibAmdIoWrite (AccessWidth8, PMIO_INDEX_PORT, &PmioAddr, NULL);
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LibAmdIoRead (AccessWidth8, PMIO_DATA_PORT, &AcpiPm1CntBlk, NULL);
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PmioAddr++;
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LibAmdIoWrite (AccessWidth8, PMIO_INDEX_PORT, &PmioAddr, NULL);
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LibAmdIoRead (AccessWidth8, PMIO_DATA_PORT, ((UINT8 *) &AcpiPm1CntBlk) + 1, NULL);
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//Get Sleep type
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LibAmdIoRead (AccessWidth16, AcpiPm1CntBlk, &SleepType, NULL);
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SleepType = SleepType & 0x1C00;
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SleepType = ((SleepType >> 10) & 7);
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return ((SleepType == 3) ? TRUE : FALSE);
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}
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#endif /* IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT) */
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