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soc/intel: Drop some HAVE_SMI_HANDLER guards 

The necessary conditionals are evaluated within
cpu/x86/Makefile.inc and there are no default
targets added unconditionally to build.

Change-Id: I694cccf6779551445b83659838749dff02aedece
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Kyösti Mälkki 2019-07-09 10:40:13 +03:00
parent fd10f773db
commit 0d9f4e9277
2 changed files with 2 additions and 2 deletions
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2
src/soc/intel/denverton_ns/Makefile.inc
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@ -19,7 +19,7 @@ subdirs-y += ../../../cpu/intel/microcode
subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/intel/turbo
subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/x86/lapic
subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/mtrr
subdirs-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/smm
subdirs-y += ../../../cpu/x86/tsc subdirs-y += ../../../cpu/x86/tsc
subdirs-y += ../../../cpu/x86/cache subdirs-y += ../../../cpu/x86/cache

2
src/soc/intel/fsp_baytrail/Makefile.inc
View File

@ -20,7 +20,7 @@ ifeq ($(CONFIG_SOC_INTEL_FSP_BAYTRAIL),y)
subdirs-y += romstage subdirs-y += romstage
subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/x86/lapic
subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/mtrr
subdirs-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/smm
subdirs-y += ../../../cpu/x86/tsc subdirs-y += ../../../cpu/x86/tsc
subdirs-y += ../../../cpu/x86/cache subdirs-y += ../../../cpu/x86/cache
subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/microcode