soc/intel/skylake: indicate voltage margining enabled/disabled

Support for voltage margining is dependent on the platform.
Enabling voltage margining puts additional constraints for
the SLP_S0# to be asserted and hence moving to S0ix state.
If the platform PMIC/VR supports PCH voltage reduction,
voltage marigining can be enabled.

Use the UPD provided by FSP to enable/disable voltage margining.

Change-Id: Iea214e9d7d6126e8367426485c6446ced63caa66
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/18469
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/soc/intel/skylake/chip.h

@@ -333,6 +333,14 @@ struct soc_intel_skylake_config {
 	 * Values: 0x0 - 4s, 0x1 - 6s, 0x2 - 8s, 0x3 - 10s, 0x4 - 12s, 0x5 - 14s
 	 */
 	u8 PmConfigPwrBtnOverridePeriod;
+
+	/*
+	 * PCH Pm Slp S0 Voltage Margining Enable
+	 * Indicates platform supports VCCPrim_Core Voltage Margining
+	 * in SLP_S0# asserted state.
+	 */
+	u8 PchPmSlpS0VmEnable;
+
 	/*
 	 * Reset Power Cycle Duration could be customized in the unit of second.
 	 * PCH HW default is 4 seconds, and range is 1~4 seconds.

src/soc/intel/skylake/chip_fsp20.c

@@ -220,6 +220,10 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	params->PchPmPwrBtnOverridePeriod =
 				config->PmConfigPwrBtnOverridePeriod;
 	params->PchPmPwrCycDur = config->PmConfigPwrCycDur;
+
+	/* Indicate whether platform supports Voltage Margining */
+	params->PchPmSlpS0VmEnable = config->PchPmSlpS0VmEnable;
+
 	params->PchSirqEnable = config->SerialIrqConfigSirqEnable;
 	params->PchSirqMode = config->SerialIrqConfigSirqMode;