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Additional early AMD8111 southbridge support for Barcelona platforms. 

Check that the SMBus controller is found and stop on an error.
Clean up and add additional path through the 8111 reset functions.


Signed-off-by: Marc Jones <marc.jones@amd.com>
Reviewed-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Myles Watson <myles@pel.cs.byu.edu> 



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3015 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Marc Jones 2007-12-19 01:36:46 +00:00
parent 8ae8c88220
commit 0da5cdeac2
2 changed files with 33 additions and 17 deletions
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38
src/southbridge/amd/amd8111/amd8111_early_ctrl.c
View File

@ -14,25 +14,33 @@ static unsigned get_sbdn(unsigned bus)
} }
static void enable_cf9_x(unsigned sbbusn, unsigned sbdn)
{
device_t dev;
uint8_t byte;
dev = PCI_DEV(sbbusn, sbdn+1, 3); //ACPI
/* enable cf9 */
byte = pci_read_config8(dev, 0x41);
byte |= (1<<6) | (1<<5);
pci_write_config8(dev, 0x41, byte);
}
static void enable_cf9(void)
{
unsigned sblk = get_sblk();
unsigned sbbusn = get_sbbusn(sblk);
unsigned sbdn = get_sbdn(sbbusn);
enable_cf9_x(sbbusn, sbdn);
}
static void hard_reset(void) static void hard_reset(void)
{ {
device_t dev;
unsigned bus;
/* Find the device.
* There can only be one 8111 on a hypertransport chain/bus.
*/
bus = get_sbbusn(get_sblk());
dev = pci_locate_device_on_bus(
PCI_ID(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_ACPI),
bus);
set_bios_reset(); set_bios_reset();
/* enable cf9 */
pci_write_config8(dev, 0x41, 0xf1);
/* reset */ /* reset */
outb(0x0e, 0x0cf9); enable_cf9();
outb(0x0e, 0x0cf9); // make sure cf9 is enabled
} }
static void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn) static void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn)

12
src/southbridge/amd/amd8111/amd8111_early_smbus.c
View File

@ -5,17 +5,25 @@
static void enable_smbus(void) static void enable_smbus(void)
{ {
device_t dev; device_t dev;
uint8_t enable;
dev = pci_locate_device(PCI_ID(0x1022, 0x746b), 0); dev = pci_locate_device(PCI_ID(0x1022, 0x746b), 0);
if (dev == PCI_DEV_INVALID) { if (dev == PCI_DEV_INVALID) {
die("SMBUS controller not found\r\n"); die("SMBUS controller not found\r\n");
} }
uint8_t enable;
print_spew("SMBus controller enabled\r\n");
pci_write_config32(dev, 0x58, SMBUS_IO_BASE | 1); pci_write_config32(dev, 0x58, SMBUS_IO_BASE | 1);
enable = pci_read_config8(dev, 0x41); enable = pci_read_config8(dev, 0x41);
pci_write_config8(dev, 0x41, enable | (1 << 7)); pci_write_config8(dev, 0x41, enable | (1 << 7));
/* check that we can see the smbus controller I/O. */
if (inw(SMBUS_IO_BASE)==0xFF){
die("SMBUS controller I/O not found\n");
}
/* clear any lingering errors, so the transaction will run */ /* clear any lingering errors, so the transaction will run */
outw(inw(SMBUS_IO_BASE + SMBGSTATUS), SMBUS_IO_BASE + SMBGSTATUS); outw(inw(SMBUS_IO_BASE + SMBGSTATUS), SMBUS_IO_BASE + SMBGSTATUS);
print_spew("SMBus controller enabled\r\n");
} }
static int smbus_recv_byte(unsigned device) static int smbus_recv_byte(unsigned device)