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intel/gm45: Fix interpretation of VT-d disable bit 

When configuring the GTT size for the integrated graphics, the state
of VT-d was read wrong. Bit 48 of CAPID0 (D0F0) is set when VT-d is
_disabled_.

In the log of a VT-d enabled roda/rk9 we have now:

[...]
VT-d enabled
[...]
IGD decoded, subtracting 32M UMA and 4M GTT
[...]

Without this patch, only 2M GTT were reported.

Change-Id: I87582c18f4769c2a05be86936d865c0d1fb35966
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3252
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Nico Huber 2013-05-14 11:02:43 +02:00 committed by Stefan Reinauer
parent 0f43af2ebb
commit 0da92863a7
1 changed files with 1 additions and 1 deletions
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2
src/northbridge/intel/gm45/igd.c
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@ -67,7 +67,7 @@ static void enable_igd(const sysinfo_t *const sysinfo, const int no_peg)
reg16 = pci_read_config16(mch_dev, D0F0_GGC); reg16 = pci_read_config16(mch_dev, D0F0_GGC);
reg16 &= 0xf00f; reg16 &= 0xf00f;
reg16 |= 0x0350; reg16 |= 0x0350;
if (capid & (1 << (48 - 32))) if (!(capid & (1 << (48 - 32))))
reg16 |= 0x0800; reg16 |= 0x0800;
pci_write_config16(mch_dev, D0F0_GGC, reg16); pci_write_config16(mch_dev, D0F0_GGC, reg16);