lynxpoint: me: Support ICC clock enables message
This message allows unused clocks to be disabled based on a devicetree setting in each mainboard. Change-Id: Ib1988cab3748490cf24028752562c64ccbce2054 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/65250 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4450 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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2017b4a44f
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@ -92,6 +92,13 @@ struct southbridge_intel_lynxpoint_config {
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/* I2C voltage select: 0=3.3V 1=1.8V */
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uint8_t sio_i2c0_voltage;
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uint8_t sio_i2c1_voltage;
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/*
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* Clock Disable Map:
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* [21:16] = CLKOUT_PCIE# 5-0
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* [24] = CLKOUT_ITPXDP
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*/
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uint32_t icc_clock_disable;
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};
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extern struct chip_operations southbridge_intel_lynxpoint_ops;
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@ -286,6 +286,24 @@ struct me_fw_version {
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u16 recovery_hot_fix;
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} __attribute__ ((packed));
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/* ICC Messages */
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#define ICC_SET_CLOCK_ENABLES 0x3
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#define ICC_API_VERSION_LYNXPOINT 0x00030000
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struct icc_header {
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u32 api_version;
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u32 icc_command;
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u32 icc_status;
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u32 length;
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u32 reserved;
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} __attribute__ ((packed));
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struct icc_clock_enables_msg {
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u32 clock_enables;
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u32 clock_mask;
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u32 no_response: 1;
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u32 reserved: 31;
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} __attribute__ ((packed));
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#define HECI_EOP_STATUS_SUCCESS 0x0
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#define HECI_EOP_PERFORM_GLOBAL_RESET 0x1
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@ -412,6 +412,30 @@ static inline int mei_sendrecv_mkhi(struct mkhi_header *mkhi,
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return 0;
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}
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static inline int mei_sendrecv_icc(struct icc_header *icc,
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void *req_data, int req_bytes,
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void *rsp_data, int rsp_bytes)
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{
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struct icc_header icc_rsp;
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/* Send header */
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if (mei_send_header(MEI_ADDRESS_ICC, MEI_HOST_ADDRESS,
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icc, sizeof(*icc), req_bytes ? 0 : 1) < 0)
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return -1;
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/* Send data if available */
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if (req_bytes && mei_send_data(MEI_ADDRESS_ICC, MEI_HOST_ADDRESS,
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req_data, req_bytes) < 0)
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return -1;
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/* Read header and data, if needed */
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if (rsp_bytes && mei_recv_msg(&icc_rsp, sizeof(icc_rsp),
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rsp_data, rsp_bytes) < 0)
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return -1;
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return 0;
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}
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/*
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* mbp give up routine. This path is taken if hfs.mpb_rdy is 0 or the read
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* state machine on the BIOS end doesn't match the ME's state machine.
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@ -610,6 +634,30 @@ void intel_me_finalize_smm(void)
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#else /* !__SMM__ */
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static int me_icc_set_clock_enables(u32 mask)
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{
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struct icc_clock_enables_msg clk = {
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.clock_enables = 0, /* Turn off specified clocks */
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.clock_mask = mask,
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.no_response = 1, /* Do not expect response */
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};
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struct icc_header icc = {
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.api_version = ICC_API_VERSION_LYNXPOINT,
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.icc_command = ICC_SET_CLOCK_ENABLES,
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.length = sizeof(clk),
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};
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/* Send request and wait for response */
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if (mei_sendrecv_icc(&icc, &clk, sizeof(clk), NULL, 0) < 0) {
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printk(BIOS_ERR, "ME: ICC SET CLOCK ENABLES message failed\n");
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return -1;
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} else {
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printk(BIOS_INFO, "ME: ICC SET CLOCK ENABLES 0x%08x\n", mask);
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}
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return 0;
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}
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/* Determine the path that we should take based on ME status */
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static me_bios_path intel_me_path(device_t dev)
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{
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@ -760,6 +808,7 @@ static int intel_me_extend_valid(device_t dev)
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/* Check whether ME is present and do basic init */
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static void intel_me_init(device_t dev)
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{
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struct southbridge_intel_lynxpoint_config *config = dev->chip_info;
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me_bios_path path = intel_me_path(dev);
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me_bios_payload mbp_data;
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@ -768,7 +817,6 @@ static void intel_me_init(device_t dev)
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if (path == ME_NORMAL_BIOS_PATH) {
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/* Validate the extend register */
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/* FIXME: force recovery mode on failure. */
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intel_me_extend_valid(dev);
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}
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@ -800,6 +848,10 @@ static void intel_me_init(device_t dev)
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}
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#endif
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/* Set clock enables according to devicetree */
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if (config && config->icc_clock_disable)
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me_icc_set_clock_enables(config->icc_clock_disable);
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/*
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* Leave the ME unlocked. It will be locked via SMI command later.
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*/
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