google/veyron_emile: adjust to the spec of emile

o. Make some gpio changes base on Emile spec.
o. Init sdmmc function.
o. Revert cpu freq reducing in recovery mode since Emile
   have more effective thermal than Mickey.
o. Revert the changes of lpddr3-samsung-2GB config.

BUG=chrome-os-partner:46658
TEST=build and boot on Emile
BRANCH=veyron

Change-Id: Ibdc2ce511c8e215c202e2067d79f4c60cdfca738
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 39e5436c8aa3353af77f62e548f48d19dc722999
Original-Change-Id: Ib2c78c9b5e3ac6620ab1772879a7ea0f7007f96e
Original-Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/307651
Original-Commit-Ready: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Tested-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/12396
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

src/mainboard/google/veyron_emile/Makefile.inc

@@ -28,6 +28,7 @@ verstage-y += reset.c
 romstage-y += boardid.c
 romstage-y += chromeos.c
 romstage-y += romstage.c
+romstage-y += sdmmc.c
 romstage-y += sdram_configs.c
 romstage-y += reset.c
 
@@ -35,6 +36,7 @@ ramstage-y += boardid.c
 ramstage-y += chromeos.c
 ramstage-y += mainboard.c
 ramstage-y += reset.c
+ramstage-y += sdmmc.c
 
 bootblock-y += memlayout.ld
 verstage-y += memlayout.ld

src/mainboard/google/veyron_emile/board.h

@@ -25,6 +25,8 @@
 
 #define GPIO_RESET	GPIO(0, B, 5)
 
+void sdmmc_power_off(void);
+void sdmmc_power_on(void);
 void setup_chromeos_gpios(void);
 
 #endif	/* __MAINBOARD_GOOGLE_VEYRON_EMILE_BOARD_H */

src/mainboard/google/veyron_emile/bootblock.c

@@ -48,7 +48,7 @@ void bootblock_mainboard_init(void)
 	if (rkclk_was_watchdog_reset())
 		reboot_from_watchdog();
 
-	gpio_output(GPIO(7, A, 0), 1);	/* Power LED */
+	gpio_output(GPIO(0, B, 3), 1);	/* Power LED */
 
 	/* Up VDD_CPU (BUCK1) to 1.4V to support max CPU frequency (1.8GHz). */
 	setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL);

src/mainboard/google/veyron_emile/mainboard.c

@@ -41,9 +41,27 @@
 
 #include "board.h"
 
+static void enable_5v_drv(void)
+{
+	gpio_output(GPIO(7, A, 3), 1);		/* 5v_drv enable */
+}
+
+static void configure_sdmmc(void)
+{
+	write32(&rk3288_grf->iomux_sdmmc0, IOMUX_SDMMC0);
+
+	/* use sdmmc0 io, disable JTAG function */
+	write32(&rk3288_grf->soc_con0, RK_CLRBITS(1 << 12));
+
+	sdmmc_power_on();
+
+	gpio_input(GPIO(7, A, 5));	/* SDMMC_DET_L */
+}
+
 static void configure_usb(void)
 {
-	gpio_output(GPIO(0, B, 4), 1);		/* USB2_PWR_EN */
+	gpio_output(GPIO(2, B, 2), 1);		/* USB3_PWR_EN */
+	gpio_output(GPIO(2, B, 3), 1);		/* USB2_PWR_EN */
 }
 
 static void configure_emmc(void)
@@ -83,14 +101,16 @@ static void configure_hdmi(void)
 	write32(&rk3288_grf->iomux_i2c5sda, IOMUX_HDMI_EDP_I2C_SDA);
 	write32(&rk3288_grf->iomux_i2c5scl, IOMUX_HDMI_EDP_I2C_SCL);
 
-	gpio_output(GPIO(7, B, 3), 1);	/* POWER_HDMI_ON */
+	gpio_output(GPIO(7, A, 2), 1);	/* POWER_HDMI_ON */
 }
 
 static void mainboard_init(device_t dev)
 {
 	gpio_output(GPIO_RESET, 0);
 
+	enable_5v_drv();
 	configure_usb();
+	configure_sdmmc();
 	configure_emmc();
 	configure_i2s();
 	configure_vop();
@@ -99,14 +119,6 @@ static void mainboard_init(device_t dev)
 	elog_init();
 	elog_add_watchdog_reset();
 	elog_add_boot_reason();
-
-	/* If recovery mode is detected, reduce frequency and voltage to reduce
-	 * heat in case machine is left unattended. chrome-os-partner:41201. */
-	if (recovery_mode_enabled())  {
-		printk(BIOS_DEBUG, "Reducing APLL freq for recovery mode.\n");
-		rkclk_configure_cpu(APLL_600_MHZ);
-		rk808_configure_buck(1, 900);
-	}
 }
 
 static void mainboard_enable(device_t dev)

src/mainboard/google/veyron_emile/romstage.c

@@ -85,6 +85,9 @@ void main(void)
 	configure_l2ctlr();
 	tsadc_init();
 
+	/* Need to power cycle SD card to ensure it is properly reset. */
+	sdmmc_power_off();
+
 	/* vdd_log 1200mv is enough for ddr run 666Mhz */
 	regulate_vdd_log(1200);
 

src/mainboard/google/veyron_emile/sdmmc.c

@@ -0,0 +1,38 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include "board.h"
+
+#include <soc/rk808.h>
+
+static void sdmmc_power(int enable)
+{
+	rk808_configure_ldo(4, enable ? 3300 : 0); /* VCC33_SD_LDO */
+	rk808_configure_ldo(5, enable ? 3300 : 0); /* VCCIO_SD */
+}
+
+void sdmmc_power_off(void)
+{
+	sdmmc_power(0);
+}
+
+void sdmmc_power_on(void)
+{
+	sdmmc_power(1);
+}

src/mainboard/google/veyron_emile/sdram_inf/sdram-lpddr3-samsung-2GB.inc

@@ -65,8 +65,7 @@
 		.mr[0] = 0x0,
 		.mr[1] = 0xC3,
 		.mr[2] = 0x6,
-		/* 40 Ohms instead of 34.3 due to bad PCB routing on Emile. */
-		.mr[3] = 0x2
+		.mr[3] = 0x1
 	},
 	.noc_timing = 0x20D266A4,
 	.noc_activate = 0x5B6,
@@ -75,5 +74,5 @@
 	.dramtype = LPDDR3,
 	.num_channels = 2,
 	.stride = 9,
-	.odt = 1,
+	.odt = 0,
 },