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This patch halts the tco timer early in the boot process on all ICH series southbridges. 

It also keeps the boot processes from rebooting through out the coreboot process.

Signed-off-by: Joseph Smith <joe@smittys.pointclark.net>
Acked-by: Corey Osgood <corey.osgood@gmail.com>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3218 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Joseph Smith 2008-04-06 04:26:19 +00:00
parent 3860404b65
commit 0dc5697220
4 changed files with 46 additions and 20 deletions
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21
src/mainboard/rca/rm4100/auto.c
View File

@ -42,6 +42,7 @@
#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
#include "southbridge/intel/i82801xx/i82801xx_early_smbus.c"
#include "southbridge/intel/i82801xx/i82801xx_early_lpc.c"
/**
* The onboard 128MB PC133 memory does not have a SPD EEPROM so the
@ -68,24 +69,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/intel/i82830/raminit.c"
#include "sdram/generic_sdram.c"
/**
* We have to disable the TCO Timer system reboot feature
* or we get several reboots through out the boot processes.
*/
static void disable_tco_timer(void)
{
device_t dev;
u8 reg8;
/* Set the LPC device statically. */
dev = PCI_DEV(0x0, 0x1f, 0x0);
/* Disable the TCO Timer system reboot feature. */
reg8 = pci_read_config8(dev, 0xd4);
reg8 |= (1 << 1);
pci_write_config8(dev, 0xd4, reg8);
}
/**
* The AC'97 Audio Controller I/O space registers are read only by default
* so we need to enable them by setting register 0x41 to 0x01.
@ -131,6 +114,6 @@ static void main(unsigned long bist)
/* ram_check(0, 640 * 1024); */
/* ram_check(130048 * 1024, 131072 * 1024); */
disable_tco_timer();
i82801xx_halt_tco_timer();
ac97_io_enable();
}

4
src/southbridge/intel/i82801xx/i82801xx.h
View File

@ -34,6 +34,7 @@ extern void i82801xx_enable(device_t dev);
#define GEN_PMCON_3 0xa4
#define PMBASE 0x40
#define PMBASE_ADDR 0x0400 /* ACPI Base Address Register */
#define ACPI_CNTL 0x44
#define BIOS_CNTL 0x4E
#define GPIO_BASE_ICH0_5 0x58 /* LPC GPIO Base Addr. Reg. (ICH0-ICH5) */
@ -68,6 +69,9 @@ extern void i82801xx_enable(device_t dev);
#define MTT 0x70
#define PCI_MAST_STS 0x82
#define TCOBASE 0x60 /* TCO Base Address Register */
#define TCO1_CNT 0x08 /* TCO1 Control Register */
/* GEN_PMCON_3 bits */
#define RTC_BATTERY_DEAD (1 << 2)
#define RTC_POWER_FAILED (1 << 1)

40
src/southbridge/intel/i82801xx/i82801xx_early_lpc.c Normal file
View File

@ -0,0 +1,40 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008 Joseph Smith <joe@smittys.pointclark.net>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*
*/
static void i82801xx_halt_tco_timer(void)
{
device_t dev;
uint16_t halt_tco_timer;
/* Set the LPC device statically. */
dev = PCI_DEV(0x0, 0x1f, 0x0);
/* Temporarily set ACPI base address (I/O space). */
pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1));
/* Temporarily enable ACPI I/O. */
pci_write_config8(dev, ACPI_CNTL, 0x10);
/* Halt the TCO timer, preventing SMI and automatic reboot */
outw(inw(PMBASE_ADDR + TCOBASE + TCO1_CNT) | (1 << 11), PMBASE_ADDR + TCOBASE + TCO1_CNT);
/* Disable ACPI I/O. */
pci_write_config8(dev, ACPI_CNTL, 0x00);
}

1
src/southbridge/intel/i82801xx/i82801xx_lpc.c
View File

@ -32,7 +32,6 @@
#include <arch/io.h>
#include "i82801xx.h"
#define PMBASE_ADDR 0x00000400 /* ACPI Base Address Register */
#define GPIO_BASE_ADDR 0x00000500 /* GPIO Base Address Register */
#define NMI_OFF 0