diff --git a/src/soc/intel/common/block/include/intelblocks/itss.h b/src/soc/intel/common/block/include/intelblocks/itss.h
index ade9756b6b..286304c031 100644
--- a/src/soc/intel/common/block/include/intelblocks/itss.h
+++ b/src/soc/intel/common/block/include/intelblocks/itss.h
@@ -3,9 +3,6 @@
 #ifndef SOC_INTEL_COMMON_BLOCK_ITSS_H
 #define SOC_INTEL_COMMON_BLOCK_ITSS_H
 
-/* Max PXRC registers in ITSS*/
-#define MAX_PXRC_CONFIG	(PCR_ITSS_PIRQH_ROUT - PCR_ITSS_PIRQA_ROUT + 1)
-
 /* PIRQA Routing Control Register*/
 #define PCR_ITSS_PIRQA_ROUT	0x3100
 /* PIRQB Routing Control Register*/
@@ -29,6 +26,7 @@
 
 #if !defined(__ACPI__)
 
+#include <southbridge/intel/common/acpi_pirq_gen.h>
 #include <stdint.h>
 
 /* Set the interrupt polarity for provided IRQ to the APIC. */
@@ -38,7 +36,7 @@ void itss_set_irq_polarity(int irq, int active_low);
 void itss_snapshot_irq_polarities(int start, int end);
 void itss_restore_irq_polarities(int start, int end);
 
-void itss_irq_init(uint8_t pch_interrupt_routing[MAX_PXRC_CONFIG]);
+void itss_irq_init(const uint8_t pch_interrupt_routing[PIRQ_COUNT]);
 void itss_clock_gate_8254(void);
 
 #endif /* !defined(__ACPI__) */
diff --git a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h
index c22eea3ad0..43a30010d3 100644
--- a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h
+++ b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h
@@ -105,5 +105,5 @@ void pch_misc_init(void);
 unsigned long southbridge_write_acpi_tables(const struct device *device,
 					    unsigned long current,
 					    struct acpi_rsdp *rsdp);
-
+const uint8_t *lpc_get_pic_pirq_routing(size_t *num);
 #endif /* _SOC_COMMON_BLOCK_LPC_LIB_H_ */
diff --git a/src/soc/intel/common/block/itss/itss.c b/src/soc/intel/common/block/itss/itss.c
index e918651e59..79ed5d0572 100644
--- a/src/soc/intel/common/block/itss/itss.c
+++ b/src/soc/intel/common/block/itss/itss.c
@@ -7,10 +7,11 @@
 #include <intelblocks/pcr.h>
 #include <soc/itss.h>
 #include <soc/pcr_ids.h>
+#include <southbridge/intel/common/acpi_pirq_gen.h>
 
-void itss_irq_init(uint8_t pch_interrupt_routing[MAX_PXRC_CONFIG])
+void itss_irq_init(const uint8_t pch_interrupt_routing[PIRQ_COUNT])
 {
-	uint32_t regs[MAX_PXRC_CONFIG/sizeof(uint32_t)] = {0};
+	uint32_t regs[PIRQ_COUNT/sizeof(uint32_t)] = {0};
 	uint8_t index, byte;
 
 	/* Fill in all the PIRx routes into one array. */
diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c
index 73a472799f..49509409e0 100644
--- a/src/soc/intel/common/block/lpc/lpc_lib.c
+++ b/src/soc/intel/common/block/lpc/lpc_lib.c
@@ -15,6 +15,7 @@
 #include <soc/irq.h>
 #include <soc/pci_devs.h>
 #include <soc/pcr_ids.h>
+#include <southbridge/intel/common/acpi_pirq_gen.h>
 
 uint16_t lpc_enable_fixed_io_ranges(uint16_t io_enables)
 {
@@ -297,6 +298,23 @@ void pch_enable_ioapic(void)
 	io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01);
 }
 
+static const uint8_t pch_interrupt_routing[PIRQ_COUNT] = {
+	[PIRQ_A] = PCH_IRQ11,
+	[PIRQ_B] = PCH_IRQ10,
+	[PIRQ_C] = PCH_IRQ11,
+	[PIRQ_D] = PCH_IRQ11,
+	[PIRQ_E] = PCH_IRQ11,
+	[PIRQ_F] = PCH_IRQ11,
+	[PIRQ_G] = PCH_IRQ11,
+	[PIRQ_H] = PCH_IRQ11,
+};
+
+const uint8_t *lpc_get_pic_pirq_routing(size_t *num)
+{
+	*num = ARRAY_SIZE(pch_interrupt_routing);
+	return pch_interrupt_routing;
+}
+
 /*
  * PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
  * 0x00 - 0000 = Reserved
@@ -321,17 +339,6 @@ void pch_enable_ioapic(void)
 void pch_pirq_init(void)
 {
 	const struct device *irq_dev;
-	uint8_t pch_interrupt_routing[MAX_PXRC_CONFIG];
-
-	pch_interrupt_routing[0] = PCH_IRQ11;
-	pch_interrupt_routing[1] = PCH_IRQ10;
-	pch_interrupt_routing[2] = PCH_IRQ11;
-	pch_interrupt_routing[3] = PCH_IRQ11;
-	pch_interrupt_routing[4] = PCH_IRQ11;
-	pch_interrupt_routing[5] = PCH_IRQ11;
-	pch_interrupt_routing[6] = PCH_IRQ11;
-	pch_interrupt_routing[7] = PCH_IRQ11;
-
 	itss_irq_init(pch_interrupt_routing);
 
 	for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {