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i82801ix: Allow configuration of SATA mode in CMOS. 

Change-Id: Ice0f0273b16a946143c038a90b61978269c1c56e
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/6409
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Vladimir Serbinenko 2014-07-29 22:35:45 +02:00 committed by Patrick Georgi
parent 8e89847af4
commit 0dd5e4395e
5 changed files with 20 additions and 13 deletions
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2
src/mainboard/emulation/qemu-q35/devicetree.cb
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@ -7,8 +7,6 @@ chip mainboard/emulation/qemu-q35
device domain 0 on
device pci 0.0 on end # northbridge (q35)
chip southbridge/intel/i82801ix
register "sata_ahci" = "1"
# present unconditionally
device pci 1f.0 on end # LPC
device pci 1f.2 on end # SATA

5
src/mainboard/roda/rk9/cmos.layout
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@ -85,7 +85,8 @@ entries
#400 8 r 0 unused
# coreboot config options: southbridge
#408 8 r 0 unused
408 1 e 9 sata_mode
#409 7 r 0 unused
# coreboot config options: bootloader
416 512 s 0 boot_devices
@ -133,6 +134,8 @@ enumerations
7 2 Keep
8 0 No
8 1 Yes
9 0 AHCI
9 1 Compatible
# -----------------------------------------------------------------
checksums

1
src/mainboard/roda/rk9/devicetree.cb
View File

@ -44,7 +44,6 @@ chip northbridge/intel/gm45
register "alt_gp_smi_en" = "0x0002"
# Set AHCI mode, enable ports 1 and 2.
register "sata_ahci" = "1"
register "sata_port_map" = "0x03"
register "sata_clock_request" = "0"
register "sata_traffic_monitor" = "0"

2
src/southbridge/intel/i82801ix/chip.h
View File

@ -70,8 +70,6 @@ struct southbridge_intel_i82801ix_config {
uint16_t alt_gp_smi_en;
/* IDE configuration */
uint32_t ide_legacy_combined;
uint32_t sata_ahci; /* If enabled, keep bit 2 of sata_enabled unset. */
uint8_t sata_port_map : 6;
int sata_clock_request : 1;
int sata_traffic_monitor : 1;

23
src/southbridge/intel/i82801ix/sata.c
View File

@ -25,6 +25,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include "i82801ix.h"
#include <pc80/mc146818rtc.h>
typedef struct southbridge_intel_i82801ix_config config_t;
@ -149,6 +150,7 @@ static void sata_init(struct device *const dev)
const u16 devid = pci_read_config16(dev, PCI_DEVICE_ID);
const int is_mobile = (devid == 0x2928) || (devid == 0x2929);
u8 sata_mode;
printk(BIOS_DEBUG, "i82801ix_sata: initializing...\n");
@ -158,6 +160,10 @@ static void sata_init(struct device *const dev)
return;
}
if (get_option(&sata_mode, "sata_mode") != CB_SUCCESS)
/* Default to AHCI */
sata_mode = 0;
/*
* TODO: In contrast to ICH7 and PCH code we don't set
* timings, dma and IDE-I/O settings here. Looks like they
@ -171,13 +177,11 @@ static void sata_init(struct device *const dev)
PCI_COMMAND_MASTER |
PCI_COMMAND_MEMORY | /* read-only in IDE modes */
PCI_COMMAND_IO);
if (!config->sata_ahci)
if (sata_mode != 0)
/* No AHCI: clear AHCI base */
pci_write_config32(dev, PCI_BASE_ADDRESS_5, 0x00000000);
if (config->ide_legacy_combined) {
printk(BIOS_DEBUG, "SATA controller in combined mode.\n");
} else if (config->sata_ahci) {
if (sata_mode == 0) {
printk(BIOS_DEBUG, "SATA controller in AHCI mode.\n");
} else {
printk(BIOS_DEBUG, "SATA controller in native mode.\n");
@ -193,7 +197,7 @@ static void sata_init(struct device *const dev)
/* Port enable. For AHCI, it's managed in memory mapped space. */
reg16 = pci_read_config16(dev, 0x92);
reg16 &= ~0x3f;
reg16 |= (1 << 15) | (config->sata_ahci ? 0x3f : config->sata_port_map);
reg16 |= (1 << 15) | ((sata_mode == 0) ? 0x3f : config->sata_port_map);
pci_write_config16(dev, 0x92, reg16);
/* SATA clock settings */
@ -218,7 +222,7 @@ static void sata_init(struct device *const dev)
}
}
if (config->sata_ahci)
if (sata_mode == 0)
sata_enable_ahci_mmap(dev, config->sata_port_map, is_mobile);
sata_program_indexed(dev, is_mobile);
@ -230,15 +234,20 @@ static void sata_enable(device_t dev)
const config_t *const config = dev->chip_info;
u16 map = 0;
u8 sata_mode;
if (!config)
return;
if (get_option(&sata_mode, "sata_mode") != CB_SUCCESS)
/* Default to AHCI */
sata_mode = 0;
/*
* Set SATA controller mode early so the resource allocator can
* properly assign IO/Memory resources for the controller.
*/
if (config->sata_ahci)
if (sata_mode == 0)
map = 0x0040 | 0x0020; /* SATA mode + all ports on D31:F2 */
map |= (config->sata_port_map ^ 0x3f) << 8;