soc/intel/cnl: Move selection of DISABLE_HECI1_AT_PRE_BOOT back to mainboard
Commit805956bce
[soc/intel/cnl: Use Kconfig to disable HECI1] moved HECI1 disablement out of mainboard devicetree and into SoC Kconfig, but in doing so inadvertently disabled HECI1 for Puff-based boards which previously had HECI1 enabled by default. To correct this, move the Kconfig selection back into the mainboard Kconfig, and set defaults to match values prior to refactoring in805956bce
. Test: run menuconfig for boards google/{drallion,hatch,puff,sarien} and ensure Disable HECI1 option defaults to selected for all except Puff. Change-Id: Idf7001fb8b0dd94677cf2b5527a61b7a29679492 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61901 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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@ -31,6 +31,9 @@ if BOARD_GOOGLE_BASEBOARD_DRALLION
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config IGNORE_IASL_MISSING_DEPENDENCY
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def_bool y
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config DISABLE_HECI1_AT_PRE_BOOT
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default y
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config CHROMEOS
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select GBB_FLAG_FORCE_DEV_SWITCH_ON
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select GBB_FLAG_FORCE_DEV_BOOT_USB
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@ -153,6 +153,9 @@ if BOARD_GOOGLE_HATCH_COMMON
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config IGNORE_IASL_MISSING_DEPENDENCY
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def_bool y
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config DISABLE_HECI1_AT_PRE_BOOT
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default y if BOARD_GOOGLE_BASEBOARD_HATCH
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config CHROMEOS
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select CHROMEOS_DRAM_PART_NUMBER_IN_CBI if !ROMSTAGE_SPD_SMBUS
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select EC_GOOGLE_CHROMEEC_SWITCHES
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@ -39,6 +39,9 @@ if BOARD_GOOGLE_BASEBOARD_SARIEN
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config IGNORE_IASL_MISSING_DEPENDENCY
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def_bool y
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config DISABLE_HECI1_AT_PRE_BOOT
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default y
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config CHROMEOS
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select GBB_FLAG_FORCE_DEV_SWITCH_ON
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select GBB_FLAG_FORCE_DEV_BOOT_USB
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@ -111,9 +111,6 @@ config CPU_SPECIFIC_OPTIONS
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select UDELAY_TSC
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select UDK_2017_BINDING
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config DISABLE_HECI1_AT_PRE_BOOT
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default y if MAINBOARD_HAS_CHROMEOS
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config MAX_CPUS
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int
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default 12
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