soc/intel/cnl: Move selection of DISABLE_HECI1_AT_PRE_BOOT back to mainboard

Commit 805956bce [soc/intel/cnl: Use Kconfig to disable HECI1]

moved HECI1 disablement out of mainboard devicetree and into SoC Kconfig,
but in doing so inadvertently disabled HECI1 for Puff-based boards which
previously had HECI1 enabled by default. To correct this, move the Kconfig
selection back into the mainboard Kconfig, and set defaults to match values
prior to refactoring in 805956bce.

Test: run menuconfig for boards google/{drallion,hatch,puff,sarien} and
ensure Disable HECI1 option defaults to selected for all except Puff.

Change-Id: Idf7001fb8b0dd94677cf2b5527a61b7a29679492
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

src/mainboard/google/drallion/Kconfig

@@ -31,6 +31,9 @@ if BOARD_GOOGLE_BASEBOARD_DRALLION
 config IGNORE_IASL_MISSING_DEPENDENCY
 	def_bool y
 
+config DISABLE_HECI1_AT_PRE_BOOT
+	default y
+
 config CHROMEOS
 	select GBB_FLAG_FORCE_DEV_SWITCH_ON
 	select GBB_FLAG_FORCE_DEV_BOOT_USB

src/mainboard/google/hatch/Kconfig

@@ -153,6 +153,9 @@ if BOARD_GOOGLE_HATCH_COMMON
 config IGNORE_IASL_MISSING_DEPENDENCY
 	def_bool y
 
+config DISABLE_HECI1_AT_PRE_BOOT
+	default y if BOARD_GOOGLE_BASEBOARD_HATCH
+
 config CHROMEOS
 	select CHROMEOS_DRAM_PART_NUMBER_IN_CBI if !ROMSTAGE_SPD_SMBUS
 	select EC_GOOGLE_CHROMEEC_SWITCHES

src/mainboard/google/sarien/Kconfig

@@ -39,6 +39,9 @@ if BOARD_GOOGLE_BASEBOARD_SARIEN
 config IGNORE_IASL_MISSING_DEPENDENCY
 	def_bool y
 
+config DISABLE_HECI1_AT_PRE_BOOT
+	default y
+
 config CHROMEOS
 	select GBB_FLAG_FORCE_DEV_SWITCH_ON
 	select GBB_FLAG_FORCE_DEV_BOOT_USB

src/soc/intel/cannonlake/Kconfig

@@ -111,9 +111,6 @@ config CPU_SPECIFIC_OPTIONS
 	select UDELAY_TSC
 	select UDK_2017_BINDING
 
-config DISABLE_HECI1_AT_PRE_BOOT
-	default y if MAINBOARD_HAS_CHROMEOS
-
 config MAX_CPUS
 	int
 	default 12