From 0de53be394deefe093b79c3b85f453023173fa98 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Wed, 26 Apr 2023 16:04:44 +0200 Subject: [PATCH] soc/amd/stoneyridge/acpi/sb_pci0_fch: report correct number of PCI buses This ports commit 8c28e51a16e1 ("soc/amd/picasso: fix host bridge bus numbers") back to Stoneyridge so that the correct number of PCI buses gets reported from PCI0's _CRS method. The MCFG ACPI table already had the correct last bus number. Signed-off-by: Felix Held Change-Id: I40121ab0e0438281192b6a0bec8dbecdc1749379 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74804 Tested-by: build bot (Jenkins) Reviewed-by: Matt DeVillier --- src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl index 6a7ed2ea42..dad8aaa2cf 100644 --- a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl @@ -111,6 +111,11 @@ Method(_CRS, 0) { Local0 -= TOM1 MM1L = Local0 + CreateWordField(CRES, ^PSB0._MAX, BMAX) + CreateWordField(CRES, ^PSB0._LEN, BLEN) + BMAX = CONFIG_ECAM_MMCONF_BUS_NUMBER - 1 + BLEN = CONFIG_ECAM_MMCONF_BUS_NUMBER + Return (CRES) /* note to change the Name buffer */ } /* end of Method(_SB.PCI0._CRS) */