soc/amd/picasso: rename PICASSO_CONSOLE_UART to AMD_SOC_CONSOLE_UART

This allows factoring out the common initialization for the integrated
UARTs.

Change-Id: I7399a13b9280b732086c6f8e6dfd9f1207d8c8ff
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48508
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/amd/mandolin/Kconfig

@@ -12,7 +12,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select AZALIA_PLUGIN_SUPPORT
 	select HAVE_ACPI_RESUME
 	select DRIVERS_UART_ACPI
-	select PICASSO_CONSOLE_UART if !AMD_LPC_DEBUG_CARD
+	select AMD_SOC_CONSOLE_UART if !AMD_LPC_DEBUG_CARD
 
 config FMDFILE
 	string
@@ -26,7 +26,7 @@ config AMD_LPC_DEBUG_CARD
 	help
 	  AMD's debug card contains an SMSC SIO1036 device which provides an
 	  I/O-mapped UART in the system. This is mutually exclusive with
-	  PICASSO_CONSOLE_UART which selects the SoC's integrated memory-mapped
+	  AMD_SOC_CONSOLE_UART which selects the SoC's integrated memory-mapped
 	  UART for coreboot console output.
 
 choice

src/mainboard/google/zork/Kconfig

@@ -34,7 +34,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select GFXUMA
 	select GOOGLE_SMBIOS_MAINBOARD_VERSION
 	select MAINBOARD_HAS_CHROMEOS
-	select PICASSO_CONSOLE_UART
+	select AMD_SOC_CONSOLE_UART
 	select MAINBOARD_HAS_I2C_TPM_CR50
 	select MAINBOARD_HAS_TPM2
 	select PCIEXP_ASPM

src/soc/amd/picasso/Kconfig

@@ -273,7 +273,7 @@ config PICASSO_ACPI_IO_BASE
 	help
 	  Base address for the ACPI registers.
 
-config PICASSO_CONSOLE_UART
+config AMD_SOC_CONSOLE_UART
 	bool "Use Picasso UART controller for console"
 	default n
 	select DRIVERS_UART_8250MEM
@@ -289,15 +289,15 @@ config PICASSO_CONSOLE_UART
 
 choice
 	prompt "UART Frequency"
-	depends on PICASSO_CONSOLE_UART
+	depends on AMD_SOC_CONSOLE_UART
-	default PICASSO_UART_48MZ
+	default AMD_SOC_UART_48MZ
 
-config PICASSO_UART_48MZ
+config AMD_SOC_UART_48MZ
 	bool "48 MHz clock"
 	help
 	  Select this option for the most compatibility.
 
-config PICASSO_UART_1_8MZ
+config AMD_SOC_UART_1_8MZ
 	bool "1.8432 MHz clock"
 	help
 	  Select this option if an old payload or Linux ttyS0 arguments
@@ -305,7 +305,7 @@ config PICASSO_UART_1_8MZ
 
 endchoice
 
-config PICASSO_UART_LEGACY
+config AMD_SOC_UART_LEGACY
 	bool "Decode legacy I/O range"
 	help
 	  Assign I/O 3F8, 2F8, etc. to a Picasso UART. A UART accessed with I/O
@@ -313,7 +313,7 @@ config PICASSO_UART_LEGACY
 	  present when this option is used.
 
 config CONSOLE_UART_BASE_ADDRESS
-	depends on CONSOLE_SERIAL && PICASSO_CONSOLE_UART
+	depends on CONSOLE_SERIAL && AMD_SOC_CONSOLE_UART
 	hex
 	default 0xfedc9000 if UART_FOR_CONSOLE = 0
 	default 0xfedca000 if UART_FOR_CONSOLE = 1

src/soc/amd/picasso/Makefile.inc

@@ -17,7 +17,7 @@ bootblock-y += bootblock.c
 bootblock-y += early_fch.c
 bootblock-y += i2c.c
 bootblock-y += uart.c
-bootblock-$(CONFIG_PICASSO_CONSOLE_UART) += uart_console.c
+bootblock-$(CONFIG_AMD_SOC_CONSOLE_UART) += uart_console.c
 bootblock-y += gpio.c
 bootblock-y += reset.c
 
@@ -27,14 +27,14 @@ romstage-y += gpio.c
 romstage-y += reset.c
 romstage-y += memmap.c
 romstage-y += uart.c
-romstage-$(CONFIG_PICASSO_CONSOLE_UART) += uart_console.c
+romstage-$(CONFIG_AMD_SOC_CONSOLE_UART) += uart_console.c
 romstage-y += psp.c
 romstage-y += mrc_cache.c
 
 verstage-y += i2c.c
 verstage_x86-y += gpio.c
 verstage_x86-y += uart.c
-verstage_x86-$(CONFIG_PICASSO_CONSOLE_UART) += uart_console.c
+verstage_x86-$(CONFIG_AMD_SOC_CONSOLE_UART) += uart_console.c
 verstage_x86-y += reset.c
 
 ramstage-y += i2c.c
@@ -53,7 +53,7 @@ ramstage-y += sata.c
 ramstage-y += memmap.c
 ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c
 ramstage-y += uart.c
-ramstage-$(CONFIG_PICASSO_CONSOLE_UART) += uart_console.c
+ramstage-$(CONFIG_AMD_SOC_CONSOLE_UART) += uart_console.c
 ramstage-y += finalize.c
 ramstage-y += soc_util.c
 ramstage-y += psp.c
@@ -67,7 +67,7 @@ ramstage-y += dmi.c
 smm-y += smihandler.c
 ifeq ($(CONFIG_DEBUG_SMI),y)
 smm-y += uart.c
-smm-$(CONFIG_PICASSO_CONSOLE_UART) += uart_console.c
+smm-$(CONFIG_AMD_SOC_CONSOLE_UART) += uart_console.c
 endif
 smm-y += gpio.c
 smm-y += psp.c

src/soc/amd/picasso/aoac.c

@@ -12,7 +12,7 @@
 		: CONFIG_UART_FOR_CONSOLE == 2 ? FCH_AOAC_DEV_UART2 \
 		: CONFIG_UART_FOR_CONSOLE == 3 ? FCH_AOAC_DEV_UART3 \
 		: -1)
-#if CONFIG(PICASSO_CONSOLE_UART) && FCH_AOAC_UART_FOR_CONSOLE == -1
+#if CONFIG(AMD_SOC_CONSOLE_UART) && FCH_AOAC_UART_FOR_CONSOLE == -1
 # error Unsupported UART_FOR_CONSOLE chosen
 #endif
 
@@ -43,13 +43,13 @@ void enable_aoac_devices(void)
 	for (i = 0; i < ARRAY_SIZE(aoac_devs); i++)
 		power_on_aoac_device(aoac_devs[i]);
 
-	if (CONFIG(PICASSO_CONSOLE_UART))
+	if (CONFIG(AMD_SOC_CONSOLE_UART))
 		power_on_aoac_device(FCH_AOAC_UART_FOR_CONSOLE);
 
 	/* Wait for AOAC devices to indicate power and clock OK */
 	for (i = 0; i < ARRAY_SIZE(aoac_devs); i++)
 		wait_for_aoac_enabled(aoac_devs[i]);
 
-	if (CONFIG(PICASSO_CONSOLE_UART))
+	if (CONFIG(AMD_SOC_CONSOLE_UART))
 		wait_for_aoac_enabled(FCH_AOAC_UART_FOR_CONSOLE);
 }

src/soc/amd/picasso/early_fch.c

@@ -39,7 +39,7 @@ void fch_pre_init(void)
 	 */
 	clear_uart_legacy_config();
 
-	if (CONFIG(PICASSO_CONSOLE_UART))
+	if (CONFIG(AMD_SOC_CONSOLE_UART))
 		set_uart_config(CONFIG_UART_FOR_CONSOLE);
 }
 

src/soc/amd/picasso/uart.c

@@ -101,7 +101,7 @@ void set_uart_config(unsigned int idx)
 
 	program_gpios(uart_info[idx].mux, 2);
 
-	if (CONFIG(PICASSO_UART_1_8MZ)) {
+	if (CONFIG(AMD_SOC_UART_1_8MZ)) {
 		uart_ctrl = sm_pci_read32(SMB_UART_CONFIG);
 		uart_ctrl |= 1 << (SMB_UART_1_8M_SHIFT + idx);
 		sm_pci_write32(SMB_UART_CONFIG, uart_ctrl);
@@ -151,7 +151,7 @@ static void uart_enable(struct device *dev)
 	if (dev->enabled) {
 		power_on_aoac_device(dev_id);
 		wait_for_aoac_enabled(dev_id);
-		if (CONFIG(PICASSO_UART_LEGACY))
+		if (CONFIG(AMD_SOC_UART_LEGACY))
 			enable_uart_legacy_decode(dev->path.mmio.addr);
 	} else {
 		power_off_aoac_device(dev_id);

src/soc/amd/picasso/uart_console.c

@@ -15,5 +15,5 @@ uintptr_t uart_platform_base(unsigned int idx)
 
 unsigned int uart_platform_refclk(void)
 {
-	return CONFIG(PICASSO_UART_48MZ) ? 48000000 : 115200 * 16;
+	return CONFIG(AMD_SOC_UART_48MZ) ? 48000000 : 115200 * 16;
 }