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mb/google/hatch: Add SoC and EC asl files in DSDT 

This implementation adds below code:

1. Add SOC ACPI code in dsdt.asl
   -> platform.asl
   -> globalnvs.asl
   -> cpu.asl
   -> northbridge.asl
   -> southbridge.asl
   -> sleepstate.asl

2. Add chromeos.asl in dsdt.asl

3. Add EC ACPI code in dsdt.asl
   -> superio.asl
   -> ec.asl

4. Remove config for WAK/PTS ACPI method as chromeec
   doesn't implement those.

BUG=b:120914069
TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot

Change-Id: Icf1b1d7e34a7e863139c3583903f3b1e2cdc8da6
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/30282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
This commit is contained in:
Aamir Bohra 2018-12-17 20:35:36 +05:30 committed by Subrata Banik
parent 3a167f56f4
commit 0dfda74408
3 changed files with 39 additions and 1 deletions
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1
src/mainboard/google/hatch/Kconfig
View File

@ -12,7 +12,6 @@ config BOARD_GOOGLE_BASEBOARD_HATCH
select MAINBOARD_HAS_SPI_TPM_CR50
select MAINBOARD_HAS_TPM2
select SOC_INTEL_CANNONLAKE_MEMCFG_INIT
select SOC_INTEL_COMMON_ACPI_EC_PTS_WAK
select SOC_INTEL_COFFEELAKE
select SYSTEM_TYPE_LAPTOP

36
src/mainboard/google/hatch/dsdt.asl
View File

@ -14,6 +14,9 @@
*/
#include <arch/acpi.h>
#include <variant/ec.h>
#include <variant/gpio.h>
DefinitionBlock(
"dsdt.aml",
"DSDT",
@ -23,4 +26,37 @@ DefinitionBlock(
0x20110725 /* OEM revision */
)
{
/* Some generic macros */
#include <soc/intel/cannonlake/acpi/platform.asl>
/* global NVS and variables */
#include <soc/intel/cannonlake/acpi/globalnvs.asl>
/* CPU */
#include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB) {
Device (PCI0)
{
#include <soc/intel/cannonlake/acpi/northbridge.asl>
#include <soc/intel/cannonlake/acpi/southbridge.asl>
}
}
#if IS_ENABLED(CONFIG_CHROMEOS)
/* Chrome OS specific */
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
#endif
/* Chipset specific sleep states */
#include <soc/intel/cannonlake/acpi/sleepstates.asl>
/* Chrome OS Embedded Controller */
Scope (\_SB.PCI0.LPCB)
{
/* ACPI code for EC SuperIO functions */
#include <ec/google/chromeec/acpi/superio.asl>
/* ACPI code for EC functions */
#include <ec/google/chromeec/acpi/ec.asl>
}
}

3
src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h
View File

@ -32,4 +32,7 @@
/* EC wake pin is LAN_WAKE# */
#define GPE_EC_WAKE GPE0_LAN_WAK
/* eSPI virtual wire reporting */
#define EC_SCI_GPI GPE0_ESPI
#endif /* BASEBOARD_GPIO_H */