soc/amd/picasso: move gpp_clk_req_setting definition to chip.h

Since this enum is only used for the devicetree settings and not for the
hardware itself, move it from the southbridge header to the chip one.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0907fc5cba9315fec5fabff67d279c6d95d1c9f0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54684
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/amd/picasso/chip.h

@@ -255,8 +255,14 @@ struct soc_amd_picasso_config {
 	/* Enable override value for tx_vboost_lvl. Range: 0 - 0x1. */
 	uint8_t usb_3_tx_vboost_lvl_en_x;
 
-	/* The array index is the general purpose PCIe clock output number. */
+	/* The array index is the general purpose PCIe clock output number. Values in here
-	enum gpp_clk_req_setting gpp_clk_config[GPP_CLK_OUTPUT_COUNT];
+	   aren't the values written to the register to have the default to be always on. */
+	enum {
+		GPP_CLK_ON,	/* GPP clock always on; default */
+		GPP_CLK_REQ,	/* GPP clock controlled by corresponding #CLK_REQx pin */
+		GPP_CLK_OFF,	/* GPP clk off */
+	} gpp_clk_config[GPP_CLK_OUTPUT_COUNT];
+
 	/* If using an external 48MHz OSC for codec, will disable internal X48M_OSC */
 	bool acp_i2s_use_external_48mhz_osc;
 

src/soc/amd/picasso/include/soc/southbridge.h

@@ -143,13 +143,6 @@
 /* IO 0xf0 NCP Error */
 #define   NCP_WARM_BOOT			BIT(7) /* Write-once */
 
-/* this is for the devicetree setting and not the values written to the register */
-enum gpp_clk_req_setting {
-	GPP_CLK_ON,	/* GPP clock always on; default */
-	GPP_CLK_REQ,	/* GPP clock controlled by corresponding #CLK_REQx pin */
-	GPP_CLK_OFF,	/* GPP clk off */
-};
-
 typedef struct aoac_devs {
 	unsigned int :7;
 	unsigned int ic2e:1; /* 7: I2C2 */