mb/google/dedede/var/metaknight: Update LTE USB port configuration
Update LTE USB port configuration at run-time after probing the firmware config. By default the concerned USB port takes the Type-A port configuration. BUG=b:186380807 BRANCH=dedede TEST=Build and boot to OS in metaknight Change-Id: I5ad5a1670adef54075923cf912fb41a1ce776155 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52960 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Evan Green <evgreen@chromium.org> Reviewed-by: Raymond Wong <wongraymond@google.com>
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@ -1,5 +1,6 @@
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# SPDX-License-Identifier: GPL-2.0-only
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# SPDX-License-Identifier: GPL-2.0-only
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ramstage-y += gpio.c
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ramstage-y += gpio.c
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ramstage-y += ramstage.c
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smm-y += variant.c
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smm-y += variant.c
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@ -69,23 +69,12 @@ chip soc/intel/jasperlake
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chip drivers/usb/acpi
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chip drivers/usb/acpi
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device usb 0.0 on
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device usb 0.0 on
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chip drivers/usb/acpi
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chip drivers/usb/acpi
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register "desc" = ""LTE""
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register "desc" = ""Multi-use Port""
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register "type" = "UPC_TYPE_INTERNAL"
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register "has_power_resource" = "1"
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H17)"
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register "reset_off_delay_ms" = "10"
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register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)"
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register "enable_delay_ms" = "20"
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device usb 2.3 on
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probe DB_PORTS DB_PORTS_LTE_HDMI
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end
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end
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chip drivers/usb/acpi
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register "desc" = ""Right Type-A Port""
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register "type" = "UPC_TYPE_A"
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register "type" = "UPC_TYPE_A"
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register "group" = "ACPI_PLD_GROUP(2, 2)"
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register "group" = "ACPI_PLD_GROUP(2, 2)"
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device usb 2.3 on
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device usb 2.3 on
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probe DB_PORTS DB_PORTS_1A_HDMI
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probe DB_PORTS DB_PORTS_1A_HDMI
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probe DB_PORTS DB_PORTS_LTE_HDMI
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end
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end
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end
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end
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chip drivers/usb/acpi
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chip drivers/usb/acpi
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@ -99,18 +88,12 @@ chip soc/intel/jasperlake
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device usb 2.6 on end
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device usb 2.6 on end
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end
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end
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chip drivers/usb/acpi
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chip drivers/usb/acpi
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register "desc" = ""LTE""
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register "desc" = ""Multi-use Port""
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register "type" = "UPC_TYPE_INTERNAL"
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device usb 3.3 on
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probe DB_PORTS DB_PORTS_LTE_HDMI
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end
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end
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chip drivers/usb/acpi
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register "desc" = ""Right Type-A Port""
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register "type" = "UPC_TYPE_USB3_A"
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register "type" = "UPC_TYPE_USB3_A"
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register "group" = "ACPI_PLD_GROUP(2, 2)"
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register "group" = "ACPI_PLD_GROUP(2, 2)"
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device usb 3.3 on
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device usb 3.3 on
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probe DB_PORTS DB_PORTS_1A_HDMI
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probe DB_PORTS DB_PORTS_1A_HDMI
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probe DB_PORTS DB_PORTS_LTE_HDMI
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end
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end
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end
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end
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end
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end
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <acpi/acpi_device.h>
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#include <baseboard/variants.h>
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#include <console/console.h>
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#include <drivers/usb/acpi/chip.h>
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#include <fw_config.h>
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#include <gpio.h>
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#include <soc/pci_devs.h>
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#define LTE_USB_PORT_ID 3
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#define LTE_USB_PORT_TYPE 2
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static struct acpi_gpio lte_reset_gpio = ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H17);
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static struct acpi_gpio lte_enable_gpio = ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10);
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static void update_xhci_devtree(void)
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{
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struct device *xhci, *hub = NULL, *port = NULL;
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struct drivers_usb_acpi_config *config;
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xhci = pcidev_path_on_root(PCH_DEVFN_XHCI);
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if (!xhci) {
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printk(BIOS_ERR, "%s: Could not locate XHCI device in DT\n", __func__);
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return;
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}
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while ((hub = dev_bus_each_child(xhci->link_list, hub)) != NULL) {
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while ((port = dev_bus_each_child(hub->link_list, port)) != NULL) {
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if (!port->chip_info || port->path.usb.port_id != LTE_USB_PORT_ID)
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continue;
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if (!fw_config_probe(FW_CONFIG(DB_PORTS, DB_PORTS_LTE_HDMI)))
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continue;
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config = port->chip_info;
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config->type = UPC_TYPE_INTERNAL;
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if (port->path.usb.port_type == LTE_USB_PORT_TYPE) {
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config->has_power_resource = 1;
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memcpy(&config->reset_gpio, <e_reset_gpio,
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sizeof(config->reset_gpio));
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config->reset_off_delay_ms = 10;
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memcpy(&config->enable_gpio, <e_enable_gpio,
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sizeof(config->enable_gpio));
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config->enable_delay_ms = 20;
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}
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}
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}
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}
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void variant_devtree_update(void)
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{
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update_xhci_devtree();
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}
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