GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/google/brya/var/lisbon: Update gpio table 

eMMC RST pin could reply on PLT_RST so we could keep GPP B3 in VIH.

BUG=b:263548436
TEST=emerge-brask coreboot

Change-Id: Iffbc9dc932325cdd2176b36795a2ff1b3690fbf8
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72941
Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This commit is contained in:
Robert Chen 2023-02-09 20:55:21 -05:00 committed by Felix Held
parent 3eb17b91da
commit 0e0f9e51c4
1 changed files with 1 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/mainboard/google/brya/variants/lisbon/gpio.c
View File

@ -25,7 +25,7 @@ static const struct pad_config override_gpio_table[] = {
/* B2 : VRALERT# ==> M2_SSD_PLA_L */
PAD_NC(GPP_B2, NONE),
/* B3 : PROC_GP2 ==> EMMC_PERST_L */
PAD_CFG_GPO(GPP_B3, 1, DEEP),
PAD_CFG_GPO_LOCK(GPP_B3, 1, LOCK_CONFIG),
/* B7 : ISH_12C1_SDA ==> PCH_I2C_MISCB_SDA */
PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG),
/* B8 : ISH_I2C1_SCL ==> PCH_I2C_MISCB_SCL */
@ -91,8 +91,6 @@ static const struct pad_config early_gpio_table[] = {
PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
/* A21 : DDPC_CTRCLK ==> EN_PP3300_EMMC */
PAD_CFG_GPO(GPP_A21, 1, DEEP),
/* B3 : PROC_GP2 ==> EMMC_PERST_L */
PAD_CFG_GPO(GPP_B3, 0, DEEP),
/* B4 : PROC_GP3 ==> SSD_PERST_L */
PAD_CFG_GPO(GPP_B4, 0, DEEP),
/* E15 : RSVD_TP ==> PCH_WP_OD */
@ -136,8 +134,6 @@ static const struct pad_config early_gpio_table[] = {
};
static const struct pad_config romstage_gpio_table[] = {
/* B3 : PROC_GP2 ==> EMMC_PERST_L */
PAD_CFG_GPO(GPP_B3, 1, DEEP),
/* B4 : PROC_GP3 ==> SSD_PERST_L */
PAD_CFG_GPO(GPP_B4, 1, DEEP),
};