Remove some additional white space to make it look nicer in nano
Signed-off-by: Anders Jenbo <anders@jenbo.dk> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5506 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -210,7 +210,7 @@ static const long register_values[] = {
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* 0x60 - 0x67
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*
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* An array of 8 byte registers, which hold the ending memory address
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* assigned to each pair of DIMMs, in 8MB granularity.
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* assigned to each pair of DIMMs, in 8MB granularity.
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*
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* 0x60 DRB0 = Total memory in row0 (in 8 MB)
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* 0x61 DRB1 = Total memory in row0+1 (in 8 MB)
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@ -433,13 +433,13 @@ static void do_ram_command(u32 command)
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static void set_dram_buffer_strength(void)
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{
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/* To give some breathing room for romcc,
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* mbsc0 doubles as drb
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* mbsc0 doubles as drb
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* mbsc1 doubles as drb1
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* mbfs0 doubles as i and reg
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*/
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uint8_t mbsc0,mbsc1,mbsc3,mbsc4,mbfs0,mbfs2,fsb;
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/* Tally how many rows between rows 0-3 and rows 4-7 are populated.
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/* Tally how many rows between rows 0-3 and rows 4-7 are populated.
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* This determines how to program MBFS and MBSC.
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*/
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uint8_t dimm03 = 0;
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@ -527,7 +527,7 @@ static void set_dram_buffer_strength(void)
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* Therefore it assumes a board with 4 slots, and will need testing
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* on boards with 3 DIMM slots.
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*/
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mbsc0 = 0x80;
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mbsc1 = 0x2a;
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mbfs2 = 0x1f;
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@ -542,36 +542,36 @@ static void set_dram_buffer_strength(void)
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mbsc4 = 0x0a;
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mbfs0 = 0x84;
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}
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if (dimm03 > 2) {
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mbsc4 = mbsc4 | 0x80;
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if (dimm03 > 2) {
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mbsc4 = mbsc4 | 0x80;
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mbsc1 = mbsc1 | 0x28;
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mbfs2 = mbfs2 | 0x40;
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mbfs0 = mbfs0 | 0x60;
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} else {
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mbsc4 = mbsc4 | 0xc0;
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} else {
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mbsc4 = mbsc4 | 0xc0;
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if (fsb == 100) {
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mbsc1 = mbsc1 | 0x3c;
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}
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}
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if (dimm47 > 2) {
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mbsc4 = mbsc4 | 0x20;
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mbsc1 = mbsc1 | 0x02;
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}
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if (dimm47 > 2) {
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mbsc4 = mbsc4 | 0x20;
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mbsc1 = mbsc1 | 0x02;
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mbsc0 = mbsc0 | 0x80;
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mbfs2 = mbfs2 | 0x20;
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mbfs0 = mbfs0 | 0x18;
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} else {
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} else {
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mbsc4 = mbsc4 | 0x30;
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if (fsb == 100) {
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mbsc1 = mbsc1 | 0x03;
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mbsc1 = mbsc1 | 0x03;
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mbsc0 = mbsc0 | 0xc0;
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}
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}
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if ((dimm03 + dimm47) > 4) {
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if ((dimm03 + dimm47) > 4) {
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mbsc0 = mbsc0 | 0x30;
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mbfs0 = mbfs0 | 0x02;
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} else {
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mbsc0 = mbsc0 | 0x2c;
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} else {
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mbsc0 = mbsc0 | 0x2c;
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}
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pci_write_config8(NB, MBSC + 0, mbsc0);
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@ -724,15 +724,15 @@ static void set_dram_row_attributes(void)
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PRINT_DEBUG("Found ");
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if (value == SPD_MEMORY_TYPE_EDO) {
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edosd |= 0x02;
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} else if (value == SPD_MEMORY_TYPE_SDRAM) {
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edosd |= 0x04;
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edosd |= 0x02;
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} else if (value == SPD_MEMORY_TYPE_SDRAM) {
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edosd |= 0x04;
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}
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PRINT_DEBUG("DIMM in slot ");
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PRINT_DEBUG_HEX8(i);
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PRINT_DEBUG("\n");
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if (edosd == 0x06) {
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if (edosd == 0x06) {
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print_err("Mixing EDO/SDRAM unsupported!\n");
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die("HALT\n");
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}
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@ -752,7 +752,7 @@ static void set_dram_row_attributes(void)
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/* Data width */
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width = spd_read_byte(device, SPD_MODULE_DATA_WIDTH_LSB);
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/* Exclude error checking data width from page size calculations */
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if (ecc) {
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value = spd_read_byte(device,
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