soc/intel/common/block/cpu: Introduce CAR_HAS_L3_PROTECTED_WAYS Kconfig

Alder Lake onwards IA SoC to select CAR_HAS_L3_PROTECTED_WAYS from SoC
Kconfig and here is modified flow as below:
Add new MSR 0xc85 IA32_L3_PROTECTED_WAYS
Update eNEM init flow:
  - Set MSR 0xC85 L3_Protected_ways = (1 << data ways) - 1
Update eNEM teardown flow:
  - Set MSR 0xC85 L3_Protected_ways = 0x00000

BUG=b:168820083
TEST=Verified filling up the entire cache with memcpy at the beginning
itself and then running the entire bootblock, verstage, debug FSP-M
without running into any issue. This proves that code caching and
eviction is working as expected in eNEM mode.

Change-Id: Idb5a9ec74c50bda371c30e13aeadbb4326887fd6
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

src/include/cpu/x86/msr.h

@@ -88,6 +88,7 @@
 #define IA32_HWP_CAPABILITIES		0x771
 #define IA32_HWP_REQUEST		0x774
 #define IA32_HWP_STATUS			0x777
+#define IA32_L3_PROTECTED_WAYS		0xc85
 #define IA32_SF_QOS_INFO		0xc87
 #define  IA32_SF_WAY_COUNT_MASK		0x3f
 #define IA32_PQR_ASSOC			0xc8f

src/soc/intel/common/block/cpu/Kconfig

@@ -78,6 +78,14 @@ config COS_MAPPED_TO_MSB
 	  On TGL and JSL platform the class of service configuration
 	  is mapped to MSB of MSR IA32_PQR_ASSOC.
 
+config CAR_HAS_L3_PROTECTED_WAYS
+	bool
+	depends on INTEL_CAR_NEM_ENHANCED
+	help
+	  On ADL and onwards platform has a newer requirement to protect
+	  L3 ways in Non-Inclusive eNEM mode. Hence, MSR 0xc85 is to program
+	  the data ways.
+
 config USE_INTEL_FSP_MP_INIT
 	bool "Perform MP Initialization by FSP"
 	default n

src/soc/intel/common/block/cpu/car/cache_as_ram.S

@@ -566,6 +566,13 @@ program_sf2:
 	xorl	%edx, %edx
 	movl	$IA32_CR_SF_QOS_MASK_1, %ecx
 	wrmsr
+#endif
+#if CONFIG(CAR_HAS_L3_PROTECTED_WAYS)
+	/* Set MSR 0xC85 L3_Protected_ways = ((1 << data ways) - 1) */
+	mov	%esi, %eax
+	xorl	%edx, %edx
+	mov	$IA32_L3_PROTECTED_WAYS, %ecx
+	wrmsr
 #endif
 	/*
 	 * Program MSR 0xC91 IA32_L3_MASK_1

src/soc/intel/common/block/cpu/car/exit_car.S

@@ -96,6 +96,13 @@ car_nem_enhanced_teardown:
 	rdmsr
 	and	$~IA32_PQR_ASSOC_MASK, %edx
 	wrmsr
+#if CONFIG(CAR_HAS_L3_PROTECTED_WAYS)
+	/* Set MSR 0xC85 L3_Protected_ways = 0x00000 */
+	mov	$IA32_L3_PROTECTED_WAYS, %ecx
+	xorl	%eax, %eax
+	xorl	%edx, %edx
+	wrmsr
+#endif
 #endif
 
 	/* Return to caller. */