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soc/intel/{ehl,jsl}: make use of Kconfig options for PRMRR size 

Migrate the last two platforms to using Kconfig through
`get_valid_prmrr_size()` instead of hardcoded values in the devicetree.

Change-Id: I93aa177f741ca8b2a2d50fae2515606b96784e83
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Michael Niewöhner 2021-09-15 12:58:11 +02:00 committed by Felix Held
parent 1ad9ff8156
commit 0e25580fe1
4 changed files with 8 additions and 22 deletions
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12
src/soc/intel/elkhartlake/chip.h
View File

@ -235,17 +235,9 @@ struct soc_intel_elkhartlake_config {
/* Enable C6 DRAM */
uint8_t enable_c6dram;
/*
* PRMRR size setting with below options
* Disable: 0x0
* 32MB: 0x2000000
* 64MB: 0x4000000
* 128 MB: 0x8000000
* 256 MB: 0x10000000
* 512 MB: 0x20000000
*/
uint32_t PrmrrSize;
uint8_t PmTimerDisabled;
/*
* SerialIO device mode selection:
* PchSerialIoDisabled,

3
src/soc/intel/elkhartlake/romstage/fsp_params.c
View File

@ -4,6 +4,7 @@
#include <console/console.h>
#include <device/device.h>
#include <fsp/util.h>
#include <intelblocks/cpulib.h>
#include <soc/iomap.h>
#include <soc/pci_devs.h>
#include <soc/romstage.h>
@ -38,7 +39,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
FSP_ARRAY_LOAD(m_cfg->PcieClkSrcUsage, config->PcieClkSrcUsage);
FSP_ARRAY_LOAD(m_cfg->PcieClkSrcClkReq, config->PcieClkSrcClkReq);
m_cfg->PrmrrSize = config->PrmrrSize;
m_cfg->PrmrrSize = get_valid_prmrr_size();
/* Disable BIOS Guard */
m_cfg->BiosGuard = 0;

12
src/soc/intel/jasperlake/chip.h
View File

@ -151,17 +151,9 @@ struct soc_intel_jasperlake_config {
/* Enable C6 DRAM */
uint8_t enable_c6dram;
/*
* PRMRR size setting with below options
* Disable: 0x0
* 32MB: 0x2000000
* 64MB: 0x4000000
* 128 MB: 0x8000000
* 256 MB: 0x10000000
* 512 MB: 0x20000000
*/
uint32_t PrmrrSize;
uint8_t PmTimerDisabled;
/*
* SerialIO device mode selection:
* PchSerialIoDisabled,

3
src/soc/intel/jasperlake/romstage/fsp_params.c
View File

@ -4,6 +4,7 @@
#include <console/console.h>
#include <device/device.h>
#include <fsp/util.h>
#include <intelblocks/cpulib.h>
#include <soc/iomap.h>
#include <soc/pci_devs.h>
#include <soc/romstage.h>
@ -72,7 +73,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
FSP_ARRAY_LOAD(m_cfg->PcieClkSrcUsage, config->PcieClkSrcUsage);
FSP_ARRAY_LOAD(m_cfg->PcieClkSrcClkReq, config->PcieClkSrcClkReq);
m_cfg->PrmrrSize = config->PrmrrSize;
m_cfg->PrmrrSize = get_valid_prmrr_size();
/* Disable BIOS Guard */
m_cfg->BiosGuard = 0;