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storm: ipq8064: enable CBFS SPI wrapper 

This change forces storm platform to use the common CBFS SPI wrapper,
which makes the SOC specific CBFS code unnecessary and requires
including SPI controller support in all coreboot stages.

BUG=chrome-os-partner:27784
TEST=manual
  . with this change and the rest of the patches coreboot on AP148
    comes up all the way to attempting to boot the payload (reading
    earlier stages from the SPI flash along the way).

Original-Change-Id: Ib468096f8e844deca11909293d90fc327aa99787
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/197932
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 794418a132b5be5a2c049f28202da3cec7ce478d)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I751c51c91f29da4f54fcfe05e7b9a2e8f956c4f2
Reviewed-on: http://review.coreboot.org/7994
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Vadim Bendebury 2014-05-01 19:37:18 -07:00 committed by Marc Jones
parent 20d3d53433
commit 0e2d9b63d7
3 changed files with 7 additions and 30 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
src/mainboard/google/storm/Kconfig
View File

@ -19,11 +19,14 @@
if BOARD_GOOGLE_STORM
config BOARD_SPECIFIC_OPTIONS # dummy
config BOARD_SPECIFIC_OPTIONS
def_bool y
select SOC_QC_IPQ806X
select BOARD_ROMSIZE_KB_4096
select COMMON_CBFS_SPI_WRAPPER
select MAINBOARD_HAS_BOOTBLOCK_INIT
select SPI_FLASH
select SPI_FLASH_SPANSION
config MAINBOARD_DIR
string

6
src/soc/qualcomm/ipq806x/Makefile.inc
View File

@ -18,21 +18,21 @@
##
bootblock-y += bootblock.c
bootblock-y += cbfs.c
bootblock-y += clock.c
bootblock-y += gpio.c
bootblock-$(CONFIG_SPI_FLASH) += spi.c
bootblock-y += timer.c
bootblock-$(CONFIG_DRIVERS_UART) += uart.c
romstage-y += cbfs.c
romstage-y += clock.c
romstage-y += gpio.c
romstage-$(CONFIG_SPI_FLASH) += spi.c
romstage-y += timer.c
romstage-$(CONFIG_DRIVERS_UART) += uart.c
ramstage-y += cbfs.c
ramstage-y += clock.c
ramstage-y += gpio.c
ramstage-$(CONFIG_SPI_FLASH) += spi.c
ramstage-y += timer.c
ramstage-$(CONFIG_DRIVERS_UART) += uart.c

26
src/soc/qualcomm/ipq806x/cbfs.c
View File

@ -1,26 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <cbfs.h> /* This driver serves as a CBFS media source. */
int init_default_cbfs_media(struct cbfs_media *media)
{
return 0;
}