arch/x86: Drop romcc bootblock
Change-Id: I79accbe1d5a554fea75fbd866995f385f718421a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37335 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Arthur Heymans
Patrick Georgi
parent
ba9b504ec5
commit
0e45b2875a
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@ -166,12 +166,6 @@ config BOOTBLOCK_DEBUG_SPINLOOP
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Add a spin (JMP .) in bootblock_crt0.S during early bootblock to wait
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for a JTAG debugger to break into the execution sequence.
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config BOOTBLOCK_MAINBOARD_INIT
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string
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config BOOTBLOCK_NORTHBRIDGE_INIT
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string
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config BOOTBLOCK_RESETS
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string
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@ -184,9 +178,6 @@ config CMOS_DEFAULT_FILE
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default "src/mainboard/$(MAINBOARDDIR)/cmos.default"
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depends on HAVE_CMOS_DEFAULT
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config BOOTBLOCK_SOUTHBRIDGE_INIT
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string
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config IOAPIC_INTERRUPTS_ON_FSB
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bool
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default y if !IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS
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@ -256,11 +247,6 @@ config BOOTBLOCK_NORMAL
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endchoice
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config BOOTBLOCK_SOURCE
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string
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default "bootblock_simple.c" if BOOTBLOCK_SIMPLE
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default "bootblock_normal.c" if BOOTBLOCK_NORMAL
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config SKIP_MAX_REBOOT_CNT_CLEAR
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bool "Do not clear reboot count after successful boot"
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depends on BOOTBLOCK_NORMAL
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@ -116,8 +116,6 @@ bootblock-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c
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bootblock-y += id.S
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$(call src-to-obj,bootblock,$(dir)/id.S): $(obj)/build.h
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ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y)
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bootblock-y += bootblock_crt0.S
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ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32),y)
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@ -128,59 +126,6 @@ endif
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bootblock-$(CONFIG_ARCH_BOOTBLOCK_X86_32) += walkcbfs.S
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else # ROMCC_BOOTBLOCK
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# x86-specific linker flags
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ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32),y)
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LDFLAGS_bootblock += -m elf_i386 --oformat elf32-i386
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else
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LDFLAGS_bootblock += -m elf_x86_64 --oformat elf64-x86-64
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endif
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# Add the assembly file that pulls in the rest of the dependencies in
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# the right order. Make sure the auto generated bootblock.inc is a proper
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# dependency. Make the same true for the linker sript.
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bootblock-y += bootblock_romcc.S
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bootblock-y += walkcbfs.S
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$(call src-to-obj,bootblock,$(dir)/bootblock_romcc.S): $(objgenerated)/bootblock.inc
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bootblock-y += bootblock.ld
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$(call src-to-obj,bootblock,$(dir)/bootblock.ld): $(objgenerated)/bootblock.ld
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bootblock_romccflags := -mcpu=i386 -O2 -D__BOOTBLOCK__
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ifeq ($(CONFIG_SSE),y)
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bootblock_romccflags := -mcpu=k7 -mno-mmx -msse -O2 -D__BOOTBLOCK__
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endif
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# This is a hack in case there are no per chipset linker files.
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$(objgenerated)/empty: build-dirs
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touch $@
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$(objgenerated)/bootblock.ld: $$(filter-out $(call src-to-obj,bootblock,src/arch/x86/bootblock.ld), $$(filter %.ld,$$(bootblock-objs))) $(objgenerated)/empty
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@printf " GEN $(subst $(obj)/,,$(@))\n"
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cat $^ >> $@.tmp
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mv $@.tmp $@
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-include $(objgenerated)/bootblock.inc.d
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$(objgenerated)/bootblock.inc: $(src)/arch/x86/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(objutil)/romcc/romcc $(OPTION_TABLE_H) $(KCONFIG_AUTOHEADER)
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# The open quote in the subst messes with syntax highlighting. Fix it - ")
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@printf " ROMCC $(subst $(obj)/,,$(@))\n"
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$(CC_bootblock) -D__ROMCC__ -D__BOOTBLOCK__ $(CPPFLAGS_bootblock) -MM -MT$(objgenerated)/bootblock.inc \
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$< > $(objgenerated)/bootblock.inc.d
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$(CC_bootblock) -D__ROMCC__ -D__BOOTBLOCK__ $(CPPFLAGS_bootblock) -E \
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$< -o $(objgenerated)/bootblock_romcc.c
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$(ROMCC) -c -S $(bootblock_romccflags) -I. $(CPPFLAGS_bootblock) $< -o $@
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# bootblock.ld is part of $(bootblock-objs)
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$(objcbfs)/bootblock.debug: $$(bootblock-objs)
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@printf " LINK $(subst $(obj)/,,$(@))\n"
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$(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) \
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$(filter-out %.ld,$(bootblock-objs)) \
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-T $(call src-to-obj,bootblock,src/arch/x86/bootblock.ld)
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endif # ROMCC_BOOTBLOCK
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endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64
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###############################################################################
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@ -223,9 +168,7 @@ ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y)
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romstage-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.c
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# gdt_init.S is included by entry32.inc when romstage is the first C
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# environment.
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ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y)
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romstage-y += gdt_init.S
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endif
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romstage-y += cbmem.c
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romstage-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c
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romstage-$(CONFIG_IDT_IN_EVERY_STAGE) += idt.S
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@ -1,23 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/x86/failover.ld>
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#include <cpu/x86/16bit/entry16.ld>
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#include <cpu/x86/16bit/reset16.ld>
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#include <arch/x86/id.ld>
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#if CONFIG(CPU_INTEL_FIRMWARE_INTERFACE_TABLE)
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#include <cpu/intel/fit/fit.ld>
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#endif
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/* Include generated .ld files. */
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#include <generated/bootblock.ld>
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@ -1,66 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <smp/node.h>
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#include <arch/bootblock_romcc.h>
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#include <pc80/mc146818rtc.h>
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#include <halt.h>
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static const char *get_fallback(const char *stagelist)
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{
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while (*stagelist)
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stagelist++;
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return ++stagelist;
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}
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static void main(unsigned long bist)
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{
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u8 boot_mode;
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const char *default_filenames =
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"normal/romstage\0fallback/romstage";
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if (boot_cpu()) {
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bootblock_mainboard_init();
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sanitize_cmos();
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boot_mode = do_normal_boot();
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} else {
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/* Questionable single byte read from CMOS.
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* Do not add any other CMOS access in the
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* bootblock for AP CPUs.
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*/
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boot_mode = boot_use_normal(cmos_read(RTC_BOOT_BYTE));
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}
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char *normal_candidate = (char *)walkcbfs("coreboot-stages");
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if (!normal_candidate)
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normal_candidate = default_filenames;
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unsigned long entry;
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if (boot_mode) {
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entry = findstage(normal_candidate);
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if (entry)
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call(entry, bist);
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}
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entry = findstage(get_fallback(normal_candidate));
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if (entry)
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call(entry, bist);
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/* duh. we're stuck */
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halt();
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}
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@ -1,49 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/*
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* This is the original bootblock used by coreboot on x86 systems. It contains
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* a monolithic code flow, assembled from the following stages:
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* - reset16.inc: the reset vector
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* - entry16.inc: protected mode setup
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* - entry32.inc: segment descriptor setup
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* - timestamp.inc: store TSC in MMX registers
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* - generated/bootblock.inc: ROMCC part of the bootblock
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*
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* This is used on platforms which select ROMCC_BOOTBLOCK, and it
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* tries to do the absolute minimum before walking CBFS and jumping to romstage.
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*
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* This file assembles the bootblock program by the order of the includes. Thus,
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* it's extremely important that one pays very careful attention to the order
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* of the includes.
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*/
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#include <arch/x86/prologue.inc>
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#include <cpu/x86/16bit/entry16.inc>
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#include <cpu/x86/16bit/reset16.inc>
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#include <cpu/x86/32bit/entry32.inc>
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#include <arch/x86/timestamp.inc>
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#if CONFIG(SSE)
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#include <cpu/x86/sse_enable.inc>
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#endif
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/*
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* This bootblock.inc file is generated by ROMCC. The above program flow
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* falls through to this point. ROMCC assumes the last function it parsed
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* is the main function and it places its instructions at the beginning of
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* the generated file. Moreover, any library/common code needed in bootblock
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* needs to come after bootblock.inc.
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*/
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#include <generated/bootblock.inc>
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@ -1,36 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <smp/node.h>
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#include <arch/bootblock_romcc.h>
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#include <pc80/mc146818rtc.h>
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#include <halt.h>
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static void main(unsigned long bist)
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{
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if (boot_cpu()) {
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bootblock_mainboard_init();
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sanitize_cmos();
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#if CONFIG(CMOS_POST)
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cmos_post_init();
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#endif
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}
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const char *target1 = "fallback/romstage";
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unsigned long entry;
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entry = findstage(target1);
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if (entry)
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call(entry, bist);
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halt();
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}
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@ -36,11 +36,9 @@
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/* Stack for CAR stages. Since it persists across all stages that
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* use CAR it can be reused. The chipset/SoC is expected to provide
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* the stack size. */
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#if !CONFIG(ROMCC_BOOTBLOCK)
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_car_stack = .;
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. += CONFIG_DCACHE_BSP_STACK_SIZE;
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_ecar_stack = .;
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#endif
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/* The pre-ram cbmem console as well as the timestamp region are fixed
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* in size. Therefore place them above the car global section so that
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* multiple stages (romstage and verstage) have a consistent
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@ -86,10 +84,6 @@
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_ebss = .;
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_car_unallocated_start = .;
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#if CONFIG(ROMCC_BOOTBLOCK)
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_car_stack = .;
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_ecar_stack = _car_region_end;
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#endif
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_car_region_end = . + CONFIG_DCACHE_RAM_SIZE - (. - _car_region_start);
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}
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@ -108,6 +102,4 @@ _bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) <= CONFIG_DC
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#if CONFIG(PAGING_IN_CACHE_AS_RAM)
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_bogus2 = ASSERT(_pagetables == ALIGN(_pagetables, 4096), "_pagetables aren't 4KiB aligned");
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#endif
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#if !CONFIG(ROMCC_BOOTBLOCK)
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_bogus3 = ASSERT(CONFIG_DCACHE_BSP_STACK_SIZE > 0x0, "BSP stack size not configured");
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#endif
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@ -1,66 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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ENTRY(_start)
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MEMORY {
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rom : ORIGIN = CONFIG_X86_RESET_VECTOR - 0xfff0, LENGTH = 64K
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}
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TARGET(binary)
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SECTIONS
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{
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/* Symbol ap_sipi_vector must be aligned to 4kB to start AP CPUs
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* with Startup IPI message without RAM. Align .rom to next 4 byte
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* boundary anyway, so no pad byte appears between _rom and _start.
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*/
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.bogus ROMLOC_MIN : {
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. = CONFIG(SIPI_VECTOR_IN_ROM) ? ALIGN(4096) : ALIGN(4);
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ROMLOC = .;
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} >rom = 0xff
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/* This section might be better named .setup */
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.rom ROMLOC : {
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_rom = .;
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*(.rom.text);
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*(.rom.data);
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*(.rom.data.*);
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*(.text);
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*(.text.*);
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*(.rodata);
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*(.rodata.*);
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_erom = .;
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} >rom = 0xff
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/* Allocation reserves extra 16 bytes here. Alignment requirements
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* may cause the total size of a section to change when the start
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* address gets applied.
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*/
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ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16) -
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(CONFIG(SIPI_VECTOR_IN_ROM) ? 4096 : 0);
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/* Post-check proper SIPI vector. */
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_bogus = ASSERT(!CONFIG(SIPI_VECTOR_IN_ROM) || (ap_sipi_vector_in_rom == 0xff),
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"Address mismatch on AP_SIPI_VECTOR");
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/DISCARD/ : {
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*(.comment)
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*(.note)
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*(.comment.*)
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*(.note.*)
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*(.eh_frame)
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*(.iplt)
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*(.rel.*)
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*(.igot.*)
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}
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}
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@ -1,45 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* This program is free software; you can redistribute it and/or modify
|
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* it under the terms of the GNU General Public License as published by
|
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* the Free Software Foundation; version 2 of the License.
|
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*
|
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* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <cpu/x86/lapic/boot_cpu.c>
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#ifdef CONFIG_BOOTBLOCK_RESETS
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#include CONFIG_BOOTBLOCK_RESETS
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#endif
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#ifdef CONFIG_BOOTBLOCK_CPU_INIT
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#include CONFIG_BOOTBLOCK_CPU_INIT
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#endif
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#ifdef CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT
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#include CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT
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#endif
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#ifdef CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT
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#include CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT
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#endif
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#ifdef CONFIG_BOOTBLOCK_MAINBOARD_INIT
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#include CONFIG_BOOTBLOCK_MAINBOARD_INIT
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#else
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static void bootblock_mainboard_init(void)
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{
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#ifdef CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT
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bootblock_northbridge_init();
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#endif
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#ifdef CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT
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bootblock_southbridge_init();
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#endif
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#ifdef CONFIG_BOOTBLOCK_CPU_INIT
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bootblock_cpu_init();
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#endif
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}
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#endif
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@ -49,7 +49,6 @@ SECTIONS
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#include EARLY_MEMLAYOUT
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#elif ENV_BOOTBLOCK
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/* arch/x86/bootblock.ld contains the logic for the ROMCC_BOOTBLOCK linking. */
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||||
BOOTBLOCK(CONFIG_X86_RESET_VECTOR - CONFIG_C_ENV_BOOTBLOCK_SIZE + 0x10,
|
||||
CONFIG_C_ENV_BOOTBLOCK_SIZE)
|
||||
|
||||
|
|
|
|||
|
|
@ -268,9 +268,7 @@ postcar-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
|
|||
postcar-$(CONFIG_GENERIC_UDELAY) += timer.c
|
||||
|
||||
# Use program.ld for all the platforms which use C fo the bootblock.
|
||||
ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y)
|
||||
bootblock-y += program.ld
|
||||
endif
|
||||
|
||||
decompressor-y += program.ld
|
||||
postcar-y += program.ld
|
||||
|
|
|
|||
Loading…
Reference in New Issue