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cpu/x86/mp_init: remove unused callback arguments

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The BSP and AP callback declarations both had an optional argument
that could be passed. In practice that functionality was never used
so drop it.

Change-Id: I47fa814a593b6c2ee164c88d255178d3fb71e8ce
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14556
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Aaron Durbin 2016-04-29 23:15:12 -05:00
parent ddf4fa0cc3
commit 0e55632661
10 changed files with 55 additions and 59 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

12
src/cpu/intel/haswell/haswell_init.c
View file

@ -772,7 +772,7 @@ static int adjust_apic_id_ht_disabled(int index, int apic_id)
return 2 * index;
}
static void relocate_and_load_microcode(void *unused)
static void relocate_and_load_microcode(void)
{
/* Relocate the SMM handler. */
smm_relocate();
@ -781,7 +781,7 @@ static void relocate_and_load_microcode(void *unused)
intel_microcode_load_unlocked(microcode_patch);
}
static void enable_smis(void *unused)
static void enable_smis(void)
{
/* Now that all APs have been relocated as well as the BSP let SMIs
* start flowing. */
@ -792,11 +792,11 @@ static void enable_smis(void *unused)
}
static struct mp_flight_record mp_steps[] = {
MP_FR_NOBLOCK_APS(relocate_and_load_microcode, NULL,
relocate_and_load_microcode, NULL),
MP_FR_BLOCK_APS(mp_initialize_cpu, NULL, mp_initialize_cpu, NULL),
MP_FR_NOBLOCK_APS(relocate_and_load_microcode,
relocate_and_load_microcode),
MP_FR_BLOCK_APS(mp_initialize_cpu, mp_initialize_cpu),
/* Wait for APs to finish initialization before proceeding. */
MP_FR_BLOCK_APS(NULL, NULL, enable_smis, NULL),
MP_FR_BLOCK_APS(NULL, enable_smis),
};
void bsp_init_and_start_aps(struct bus *cpu_bus)

6
src/cpu/x86/mp_init.c
View file

@ -129,7 +129,7 @@ static void ap_do_flight_plan(void)
barrier_wait(&rec->barrier);
if (rec->ap_call != NULL) {
rec->ap_call(rec->ap_arg);
rec->ap_call();
}
}
}
@ -477,7 +477,7 @@ static int bsp_do_flight_plan(struct mp_params *mp_params)
}
if (rec->bsp_call != NULL) {
rec->bsp_call(rec->bsp_arg);
rec->bsp_call();
}
release_barrier(&rec->barrier);
@ -563,7 +563,7 @@ int mp_init(struct bus *cpu_bus, struct mp_params *p)
return bsp_do_flight_plan(p);
}
void mp_initialize_cpu(void *unused)
void mp_initialize_cpu(void)
{
/* Call back into driver infrastructure for the AP initialization. */
struct cpu_info *info = cpu_info();

18
src/include/cpu/x86/mp.h
View file

@ -28,7 +28,7 @@ static inline void mfence(void)
__asm__ __volatile__("mfence\t\n": : :"memory");
}
typedef void (*mp_callback_t)(void *arg);
typedef void (*mp_callback_t)(void);
/*
* A mp_flight_record details a sequence of calls for the APs to perform
@ -47,26 +47,22 @@ struct mp_flight_record {
atomic_t barrier;
atomic_t cpus_entered;
mp_callback_t ap_call;
void *ap_arg;
mp_callback_t bsp_call;
void *bsp_arg;
} __attribute__((aligned(CACHELINE_SIZE)));
#define _MP_FLIGHT_RECORD(barrier_, ap_func_, ap_arg_, bsp_func_, bsp_arg_) \
#define _MP_FLIGHT_RECORD(barrier_, ap_func_, bsp_func_) \
{ \
.barrier = ATOMIC_INIT(barrier_), \
.cpus_entered = ATOMIC_INIT(0), \
.ap_call = ap_func_, \
.ap_arg = ap_arg_, \
.bsp_call = bsp_func_, \
.bsp_arg = bsp_arg_, \
}
#define MP_FR_BLOCK_APS(ap_func_, ap_arg_, bsp_func_, bsp_arg_) \
_MP_FLIGHT_RECORD(0, ap_func_, ap_arg_, bsp_func_, bsp_arg_)
#define MP_FR_BLOCK_APS(ap_func_, bsp_func_) \
_MP_FLIGHT_RECORD(0, ap_func_, bsp_func_)
#define MP_FR_NOBLOCK_APS(ap_func_, ap_arg_, bsp_func_, bsp_arg_) \
_MP_FLIGHT_RECORD(1, ap_func_, ap_arg_, bsp_func_, bsp_arg_)
#define MP_FR_NOBLOCK_APS(ap_func_, bsp_func_) \
_MP_FLIGHT_RECORD(1, ap_func_, bsp_func_)
/* The mp_params structure provides the arguments to the mp subsystem
* for bringing up APs. */
@ -108,7 +104,7 @@ int mp_init(struct bus *cpu_bus, struct mp_params *params);
*/
/* Calls cpu_initialize(info->index) which calls the coreboot CPU drivers. */
void mp_initialize_cpu(void *unused);
void mp_initialize_cpu(void);
/* Returns apic id for coreboot cpu number or < 0 on failure. */
int mp_get_apic_id(int cpu_slot);

2
src/soc/intel/apollolake/cpu.c
View file

@ -71,7 +71,7 @@ static void bsp_pre_mp_setup(void)
*/
static struct mp_flight_record flight_plan[] = {
/* NOTE: MTRR solution must be calculated before firing up the APs */
MP_FR_NOBLOCK_APS(mp_initialize_cpu, NULL, mp_initialize_cpu, NULL),
MP_FR_NOBLOCK_APS(mp_initialize_cpu, mp_initialize_cpu),
};
void apollolake_init_cpus(device_t dev)

14
src/soc/intel/baytrail/cpu.c
View file

@ -32,14 +32,14 @@
#include <soc/ramstage.h>
#include <soc/smm.h>
static void smm_relocate(void *unused);
static void enable_smis(void *unused);
static void smm_relocate(void);
static void enable_smis(void);
static struct mp_flight_record mp_steps[] = {
MP_FR_BLOCK_APS(smm_relocate, NULL, smm_relocate, NULL),
MP_FR_BLOCK_APS(mp_initialize_cpu, NULL, mp_initialize_cpu, NULL),
MP_FR_BLOCK_APS(smm_relocate, smm_relocate),
MP_FR_BLOCK_APS(mp_initialize_cpu, mp_initialize_cpu),
/* Wait for APs to finish initialization before proceeding. */
MP_FR_BLOCK_APS(NULL, NULL, enable_smis, NULL),
MP_FR_BLOCK_APS(NULL, enable_smis),
};
/* The APIC id space on Bay Trail is sparse. Each id is separated by 2. */
@ -278,7 +278,7 @@ static int smm_load_handlers(void)
return 0;
}
static void smm_relocate(void *unused)
static void smm_relocate(void)
{
const struct pattrs *pattrs = pattrs_get();
@ -298,7 +298,7 @@ static void smm_relocate(void *unused)
intel_microcode_load_unlocked(pattrs->microcode_patch);
}
static void enable_smis(void *unused)
static void enable_smis(void)
{
southcluster_smm_enable_smi();
}

20
src/soc/intel/braswell/cpu.c
View file

@ -33,16 +33,16 @@
#include <soc/smm.h>
#include <stdlib.h>
static void smm_relocate(void *unused);
static void enable_smis(void *unused);
static void pre_smm_relocation(void *unused);
static void smm_relocate(void);
static void enable_smis(void);
static void pre_smm_relocation(void);
static struct mp_flight_record mp_steps[] = {
MP_FR_BLOCK_APS(pre_smm_relocation, NULL, pre_smm_relocation, NULL),
MP_FR_BLOCK_APS(smm_relocate, NULL, smm_relocate, NULL),
MP_FR_BLOCK_APS(mp_initialize_cpu, NULL, mp_initialize_cpu, NULL),
MP_FR_BLOCK_APS(pre_smm_relocation, pre_smm_relocation),
MP_FR_BLOCK_APS(smm_relocate, smm_relocate),
MP_FR_BLOCK_APS(mp_initialize_cpu, mp_initialize_cpu),
/* Wait for APs to finish initialization before proceeding. */
MP_FR_BLOCK_APS(NULL, NULL, enable_smis, NULL),
MP_FR_BLOCK_APS(NULL, enable_smis),
};
/* The APIC id space is sparse. Each id is separated by 2. */
@ -299,7 +299,7 @@ static int smm_load_handlers(void)
return 0;
}
static void pre_smm_relocation(void *unused)
static void pre_smm_relocation(void)
{
const struct pattrs *pattrs = pattrs_get();
msr_t msr_value;
@ -310,7 +310,7 @@ static void pre_smm_relocation(void *unused)
intel_microcode_load_unlocked(pattrs->microcode_patch);
}
static void smm_relocate(void *unused)
static void smm_relocate(void)
{
const struct pattrs *pattrs = pattrs_get();
@ -330,7 +330,7 @@ static void smm_relocate(void *unused)
intel_microcode_load_unlocked(pattrs->microcode_patch);
}
static void enable_smis(void *unused)
static void enable_smis(void)
{
southcluster_smm_enable_smi();
}

12
src/soc/intel/broadwell/cpu.c
View file

@ -619,7 +619,7 @@ static int adjust_apic_id_ht_disabled(int index, int apic_id)
return 2 * index;
}
static void relocate_and_load_microcode(void *unused)
static void relocate_and_load_microcode(void)
{
/* Relocate the SMM handler. */
smm_relocate();
@ -628,7 +628,7 @@ static void relocate_and_load_microcode(void *unused)
intel_microcode_load_unlocked(microcode_patch);
}
static void enable_smis(void *unused)
static void enable_smis(void)
{
/* Now that all APs have been relocated as well as the BSP let SMIs
* start flowing. */
@ -639,11 +639,11 @@ static void enable_smis(void *unused)
}
static struct mp_flight_record mp_steps[] = {
MP_FR_NOBLOCK_APS(relocate_and_load_microcode, NULL,
relocate_and_load_microcode, NULL),
MP_FR_BLOCK_APS(mp_initialize_cpu, NULL, mp_initialize_cpu, NULL),
MP_FR_NOBLOCK_APS(relocate_and_load_microcode,
relocate_and_load_microcode),
MP_FR_BLOCK_APS(mp_initialize_cpu, mp_initialize_cpu),
/* Wait for APs to finish initialization before proceeding. */
MP_FR_BLOCK_APS(NULL, NULL, enable_smis, NULL),
MP_FR_BLOCK_APS(NULL, enable_smis),
};
static struct device_operations cpu_dev_ops = {

16
src/soc/intel/fsp_baytrail/cpu.c
View file

@ -33,18 +33,18 @@
#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
#include <soc/smm.h>
static void smm_relocate(void *unused);
static void enable_smis(void *unused);
static void smm_relocate(void);
static void enable_smis(void);
static struct mp_flight_record mp_steps[] = {
MP_FR_BLOCK_APS(smm_relocate, NULL, smm_relocate, NULL),
MP_FR_BLOCK_APS(mp_initialize_cpu, NULL, mp_initialize_cpu, NULL),
MP_FR_BLOCK_APS(smm_relocate, smm_relocate),
MP_FR_BLOCK_APS(mp_initialize_cpu, mp_initialize_cpu),
/* Wait for APs to finish initialization before proceeding. */
MP_FR_BLOCK_APS(NULL, NULL, enable_smis, NULL),
MP_FR_BLOCK_APS(NULL, enable_smis),
};
#else /* CONFIG_HAVE_SMI_HANDLER */
static struct mp_flight_record mp_steps[] = {
MP_FR_BLOCK_APS(mp_initialize_cpu, NULL, mp_initialize_cpu, NULL),
MP_FR_BLOCK_APS(mp_initialize_cpu, mp_initialize_cpu),
};
#endif
@ -252,7 +252,7 @@ static int smm_load_handlers(void)
return 0;
}
static void smm_relocate(void *unused)
static void smm_relocate(void)
{
/* Load relocation and permanent handler. */
@ -268,7 +268,7 @@ static void smm_relocate(void *unused)
smm_initiate_relocation();
}
static void enable_smis(void *unused)
static void enable_smis(void)
{
southcluster_smm_enable_smi();
}

2
src/soc/intel/fsp_broadwell_de/cpu.c
View file

@ -30,7 +30,7 @@
static void configure_mca(void);
static struct mp_flight_record mp_steps[] = {
MP_FR_BLOCK_APS(mp_initialize_cpu, NULL, mp_initialize_cpu, NULL),
MP_FR_BLOCK_APS(mp_initialize_cpu, mp_initialize_cpu),
};
static int adjust_apic_id(int index, int apic_id)

12
src/soc/intel/skylake/cpu.c
View file

@ -391,7 +391,7 @@ static int adjust_apic_id_ht_disabled(int index, int apic_id)
return 2 * index;
}
static void relocate_and_load_microcode(void *unused)
static void relocate_and_load_microcode(void)
{
/* Relocate the SMM handler. */
smm_relocate();
@ -400,7 +400,7 @@ static void relocate_and_load_microcode(void *unused)
intel_microcode_load_unlocked(microcode_patch);
}
static void enable_smis(void *unused)
static void enable_smis(void)
{
/*
* Now that all APs have been relocated as well as the BSP let SMIs
@ -415,13 +415,13 @@ static void enable_smis(void *unused)
}
static struct mp_flight_record mp_steps[] = {
MP_FR_NOBLOCK_APS(relocate_and_load_microcode, NULL,
relocate_and_load_microcode, NULL),
MP_FR_NOBLOCK_APS(relocate_and_load_microcode,
relocate_and_load_microcode),
#if IS_ENABLED(CONFIG_SMP)
MP_FR_BLOCK_APS(mp_initialize_cpu, NULL, mp_initialize_cpu, NULL),
MP_FR_BLOCK_APS(mp_initialize_cpu, mp_initialize_cpu),
/* Wait for APs to finish initialization before proceeding. */
#endif
MP_FR_BLOCK_APS(NULL, NULL, enable_smis, NULL),
MP_FR_BLOCK_APS(NULL, enable_smis),
};
static struct device_operations cpu_dev_ops = {