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soc/intel/alderlake: Fix DDR5 channel mapping 

DDR5 memory modules have two separate 32-bit channels (40-bit on ECC
memory modules), and the SPD info refers to one channel: the primary
bus width is 32 (or 40) bits and the "DIMM size" is halved. On Alder
Lake, there are 2 memory controllers with 4 32-bit channels each for
DDR5. FSP has 16 positions to store SPD data, some of which are only
used with LPDDR4/LPDDR5.

To try to make things less confusing, FSP abstracts the DDR5 channels
so that the configuration works like on DDR4. This is done by copying
each DIMM's SPD data to the other half-channel. Thus, fix the wrapper
parameters for DDR5 accordingly.

Tested on AlderLake-P DDR5 RVP (board ID 0x12), both DIMM slots now
function properly. Without this patch, only the top slot would work.

Change-Id: I5f01cd77388b89ba34d91c2dc5fb843fe9db9826
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66608
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Angel Pons 2022-08-10 20:38:06 +02:00 committed by Tim Wawrzynczak
parent a8cf2f2d73
commit 0e7cf3d81d
1 changed files with 6 additions and 8 deletions
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14
src/soc/intel/alderlake/meminit.c
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@ -62,18 +62,16 @@ static const struct soc_mem_cfg soc_mem_cfg[] = {
.num_phys_channels = DDR5_CHANNELS,
.phys_to_mrc_map = {
[0] = 0,
[1] = 1,
[2] = 4,
[3] = 5,
[1] = 4,
},
.md_phy_masks = {
/*
* Physical channels 0 and 1 are populated in case of
* half-populated configurations.
* Only channel 0 is populated in case of half-populated
* configuration.
*/
.half_channel = BIT(0) | BIT(1),
/* In mixed topologies, channels 2 and 3 are always memory-down. */
.mixed_topo = BIT(2) | BIT(3),
.half_channel = BIT(0),
/* In mixed topologies, channel 1 is always memory-down. */
.mixed_topo = BIT(1),
},
},
[MEM_TYPE_LP4X] = {