From 0e834a94556854751a321d28acf20605c75aa4da Mon Sep 17 00:00:00 2001 From: Casper Chang Date: Fri, 4 Mar 2022 14:08:01 +0800 Subject: [PATCH] mb/google/brya/var/primus{4es}: add enable pin to rtd3-cold Currently the BayHub eMMC controller is only going into its reset state when the RTD3 sequence is initiated. This causes it to still consume too much power in suspend states. This CL adds the power enable GPIO into the RTD3 sequence as well, which will turn off the eMMC controller (a true D3cold state) during the RTD3 sequence. BUG=b:222436260 TEST=USE="project_primus" emerge-brya coreboot chromeos-bootimage test suspend stress 100 cycles passed on primus. Signed-off-by: Casper Chang Change-Id: I2fec6a30707fb1a258cdcc73b0ce38252b6f77c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62586 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/mainboard/google/brya/variants/primus/overridetree.cb | 1 + src/mainboard/google/brya/variants/primus4es/overridetree.cb | 1 + 2 files changed, 2 insertions(+) diff --git a/src/mainboard/google/brya/variants/primus/overridetree.cb b/src/mainboard/google/brya/variants/primus/overridetree.cb index 36fee91a3d..6b88822248 100644 --- a/src/mainboard/google/brya/variants/primus/overridetree.cb +++ b/src/mainboard/google/brya/variants/primus/overridetree.cb @@ -144,6 +144,7 @@ chip soc/intel/alderlake device ref pcie_rp3 on chip soc/intel/common/block/pcie/rtd3 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B3)" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E20)" register "srcclk_pin" = "6" device generic 0 alias emmc_rtd3 on end end diff --git a/src/mainboard/google/brya/variants/primus4es/overridetree.cb b/src/mainboard/google/brya/variants/primus4es/overridetree.cb index 77218b09d5..d6400c2462 100644 --- a/src/mainboard/google/brya/variants/primus4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/primus4es/overridetree.cb @@ -138,6 +138,7 @@ chip soc/intel/alderlake device ref pcie_rp3 on chip soc/intel/common/block/pcie/rtd3 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B3)" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E20)" register "srcclk_pin" = "6" device generic 0 alias emmc_rtd3 on end end