Move TPM code out of chromeos

This code is not specific to ChromeOS and is useful outside of it.
Like with small modifications it can be used to disable TPM altogether.

Change-Id: I8c6baf0a1f7c67141f30101a132ea039b0d09819
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10269
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/cpu/intel/haswell/romstage.c

@@ -45,7 +45,7 @@
 #include "northbridge/intel/haswell/raminit.h"
 #include "southbridge/intel/lynxpoint/pch.h"
 #include "southbridge/intel/lynxpoint/me.h"
-
+#include <tpm.h>
 
 static inline void reset_system(void)
 {
@@ -276,9 +276,9 @@ void romstage_common(const struct romstage_params *params)
 		printk(BIOS_DEBUG, "Romstage handoff structure not added!\n");
 
 	post_code(0x3f);
-#if CONFIG_CHROMEOS
+	if (CONFIG_LPC_TPM) {
-	init_chromeos(boot_mode);
+		init_tpm(wake_from_s3);
-#endif
+	}
 	timestamp_add_now(TS_END_ROMSTAGE);
 }
 

src/drivers/pc80/tpm/Kconfig

@@ -1,6 +1,13 @@
-config LPC_TPM
+config MAINBOARD_HAS_LPC_TPM
        bool
        default n
+       help
+         Board has TPM support
+
+config LPC_TPM
+	bool "Enable TPM support"
+	depends on MAINBOARD_HAS_LPC_TPM
+	default n
 	help
 	  Enable this option to enable LPC TPM support in coreboot.
 
@@ -15,3 +22,18 @@ config TPM_TIS_BASE_ADDRESS
 	  The default is specified by the TCG PC Client Specific TPM
 	  Interface Specification 1.2 and should not be changed unless
 	  the TPM being used does not conform to TPM TIS 1.2.
+
+config TPM_INIT_FAILURE_IS_FATAL
+	bool
+	default n
+	depends on LPC_TPM
+	help
+	  What to do if TPM init failed. If true, force a hard reset,
+	  otherwise just log error message to console.
+
+config SKIP_TPM_STARTUP_ON_NORMAL_BOOT
+	bool
+	default n
+	depends on LPC_TPM
+	help
+	  Skip TPM init on normal boot. Useful if payload does TPM init.

src/drivers/pc80/tpm/Makefile.inc

@@ -1,2 +1,3 @@
 romstage-$(CONFIG_LPC_TPM) += tpm.c
 ramstage-$(CONFIG_LPC_TPM) += tpm.c
+romstage-$(CONFIG_LPC_TPM) += romstage.c

src/drivers/pc80/tpm/romstage.c

@@ -23,10 +23,8 @@
 #include <arch/acpi.h>
 #include <tpm.h>
 #include <reset.h>
-#include "chromeos.h"
 
 //#define EXTRA_LOGGING
-#define UBOOT_DOES_TPM_STARTUP
 
 #define TPM_LARGE_ENOUGH_COMMAND_SIZE 256	/* saves space in the firmware */
 
@@ -40,11 +38,6 @@
 #define TPM_E_NEEDS_SELFTEST     ((u32)(TPM_E_NON_FATAL + 1))
 #define TPM_E_DOING_SELFTEST     ((u32)(TPM_E_NON_FATAL + 2))
 
-#if CONFIG_NO_TPM_RESUME
-static void init_vboot(int bootmode)
-{
-}
-#else
 static const struct {
 	u8 buffer[12];
 } tpm_resume_cmd = {
@@ -183,22 +176,21 @@ static u32 TlclSendReceive(const u8 * request, u8 * response, int max_length)
 	return result;
 }
 
-static void init_vboot(int bootmode)
+void init_tpm(int s3resume)
 {
 	u32 result;
 	u8 response[TPM_LARGE_ENOUGH_COMMAND_SIZE];
 
-#ifdef UBOOT_DOES_TPM_STARTUP
 	/* Doing TPM startup when we're not coming in on the S3 resume path
 	 * saves us roughly 20ms in boot time only. This does not seem to
 	 * be worth an API change to vboot_reference-firmware right now, so
 	 * let's keep the code around, but just bail out early:
 	 */
-	if (bootmode != 2)
+	if (s3resume ? CONFIG_NO_TPM_RESUME
+	    : CONFIG_SKIP_TPM_STARTUP_ON_NORMAL_BOOT)
 		return;
-#endif
 
-	printk(BIOS_DEBUG, "Verified boot TPM initialization.\n");
+	printk(BIOS_DEBUG, "TPM initialization.\n");
 
 	printk(BIOS_SPEW, "TPM: Init\n");
 	if (tis_init())
@@ -209,7 +201,7 @@ static void init_vboot(int bootmode)
 		return;
 
 
-	if (bootmode == 2) {
+	if (s3resume) {
 		/* S3 Resume */
 		printk(BIOS_SPEW, "TPM: Resume\n");
 		result = TlclSendReceive(tpm_resume_cmd.buffer,
@@ -232,17 +224,13 @@ static void init_vboot(int bootmode)
 		return;
 	}
 
-#if !MOCK_TPM
+	printk(BIOS_ERR, "TPM: Error code 0x%x.\n", result);
-	printk(BIOS_ERR, "TPM: Error code 0x%x. Hard reset!\n", result);
+
+	if (CONFIG_TPM_INIT_FAILURE_IS_FATAL) {
+		printk(BIOS_ERR, "Hard reset!\n");
 		post_code(POST_TPM_FAILURE);
 		if (IS_ENABLED(CONFIG_CONSOLE_CBMEM_DUMP_TO_UART))
 			cbmem_dump_console();
 		hard_reset();
-#endif
+	}
-}
-#endif
-
-void init_chromeos(int bootmode)
-{
-	init_vboot(bootmode);
 }

src/include/tpm.h

@@ -66,4 +66,6 @@ int tis_close(void);
 int tis_sendrecv(const u8 *sendbuf, size_t send_size, u8 *recvbuf,
 			size_t *recv_len);
 
+void init_tpm(int s3resume);
+
 #endif /* TPM_H_ */

src/mainboard/google/bolt/Kconfig

@@ -16,6 +16,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select MMCONF_SUPPORT
 	select HAVE_SMI_HANDLER
 	select MAINBOARD_HAS_CHROMEOS
+	select MAINBOARD_HAS_LPC_TPM
 	select EXTERNAL_MRC_BLOB
 	select INTEL_INT15
 	select CHROMEOS_VBNV_CMOS

src/mainboard/google/butterfly/Kconfig

@@ -13,6 +13,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_CMOS_DEFAULT
 	select HAVE_ACPI_RESUME
 	select MAINBOARD_HAS_CHROMEOS
+	select MAINBOARD_HAS_LPC_TPM
 	select INTEL_INT15
 	select CHROMEOS_VBNV_CMOS
 

src/mainboard/google/falco/Kconfig

@@ -17,6 +17,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select MMCONF_SUPPORT
 	select HAVE_SMI_HANDLER
 	select MAINBOARD_HAS_CHROMEOS
+	select MAINBOARD_HAS_LPC_TPM
 	select EXTERNAL_MRC_BLOB
 	select MAINBOARD_HAS_NATIVE_VGA_INIT
 	select MAINBOARD_DO_NATIVE_VGA_INIT

src/mainboard/google/link/Kconfig

@@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_OPTION_TABLE
 	select HAVE_ACPI_RESUME
 	select MAINBOARD_HAS_CHROMEOS
+	select MAINBOARD_HAS_LPC_TPM
 	select SERIRQ_CONTINUOUS_MODE
 	select MAINBOARD_HAS_NATIVE_VGA_INIT
 	select CHROMEOS_VBNV_CMOS

src/mainboard/google/link/romstage.c

@@ -41,9 +41,7 @@
 #include <cpu/x86/msr.h>
 #include <halt.h>
 #include "gpio.h"
-#if CONFIG_CHROMEOS
+#include <tpm.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-#endif
 #include <cbfs.h>
 
 #include <southbridge/intel/bd82x6x/chip.h>
@@ -246,8 +244,9 @@ void main(unsigned long bist)
 	northbridge_romstage_finalize(boot_mode==2);
 
 	post_code(0x3f);
-#if CONFIG_CHROMEOS
+	if (CONFIG_LPC_TPM) {
-	init_chromeos(boot_mode);
+		init_tpm(boot_mode == 2);
-#endif
+	}
+
 	timestamp_add_now(TS_END_ROMSTAGE);
 }

src/mainboard/google/panther/Kconfig

@@ -15,6 +15,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select MMCONF_SUPPORT
 	select HAVE_SMI_HANDLER
 	select MAINBOARD_HAS_CHROMEOS
+	select MAINBOARD_HAS_LPC_TPM
 	select EXTERNAL_MRC_BLOB
 	select INTEL_INT15
 	select PHYSICAL_REC_SWITCH

src/mainboard/google/parrot/Kconfig

@@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_OPTION_TABLE
 	select HAVE_ACPI_RESUME
 	select MAINBOARD_HAS_CHROMEOS
+	select MAINBOARD_HAS_LPC_TPM
 	select INTEL_INT15
 	select CHROMEOS_VBNV_CMOS
 

src/mainboard/google/parrot/romstage.c

@@ -39,10 +39,8 @@
 #include <cpu/x86/msr.h>
 #include <halt.h>
 #include "gpio.h"
-#if CONFIG_CHROMEOS
-#include <vendorcode/google/chromeos/chromeos.h>
-#endif
 #include <cbfs.h>
+#include <tpm.h>
 #include "ec/compal/ene932/ec.h"
 
 static void pch_enable_lpc(void)
@@ -197,8 +195,8 @@ void main(unsigned long bist)
 	northbridge_romstage_finalize(boot_mode==2);
 
 	post_code(0x3f);
-#if CONFIG_CHROMEOS
+	if (CONFIG_LPC_TPM) {
-	init_chromeos(boot_mode);
+		init_tpm(boot_mode == 2);
-#endif
+	}
 	timestamp_add_now(TS_END_ROMSTAGE);
 }

src/mainboard/google/peppy/Kconfig

@@ -17,6 +17,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select MMCONF_SUPPORT
 	select HAVE_SMI_HANDLER
 	select MAINBOARD_HAS_CHROMEOS
+	select MAINBOARD_HAS_LPC_TPM
 	select EXTERNAL_MRC_BLOB
 	select MAINBOARD_HAS_NATIVE_VGA_INIT
 	select MAINBOARD_DO_NATIVE_VGA_INIT

src/mainboard/google/rambi/Kconfig

@@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select HAVE_OPTION_TABLE
 	select HAVE_ACPI_RESUME
 	select MAINBOARD_HAS_CHROMEOS
+	select MAINBOARD_HAS_LPC_TPM
 	select ALWAYS_LOAD_OPROM
 	select CHROMEOS_VBNV_CMOS
 

src/mainboard/google/samus/Kconfig

@@ -15,6 +15,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select MMCONF_SUPPORT
 	select HAVE_SMI_HANDLER
 	select MAINBOARD_HAS_CHROMEOS
+	select MAINBOARD_HAS_LPC_TPM
 	select EXTERNAL_MRC_BLOB
 	select CHROMEOS_RAMOOPS_DYNAMIC
 	select INTEL_INT15

src/mainboard/google/slippy/Kconfig

@@ -16,6 +16,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select MMCONF_SUPPORT
 	select HAVE_SMI_HANDLER
 	select MAINBOARD_HAS_CHROMEOS
+	select MAINBOARD_HAS_LPC_TPM
 	select EXTERNAL_MRC_BLOB
 	select INTEL_DP
 	select INTEL_DDI

src/mainboard/google/stout/Kconfig

@@ -13,6 +13,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_CMOS_DEFAULT
 	select HAVE_ACPI_RESUME
 	select MAINBOARD_HAS_CHROMEOS
+	select MAINBOARD_HAS_LPC_TPM
 	select INTEL_INT15
 	select CHROMEOS_VBNV_CMOS
 

src/mainboard/google/stout/romstage.c

@@ -40,9 +40,7 @@
 #include <halt.h>
 #include "gpio.h"
 #include <bootmode.h>
-#if CONFIG_CHROMEOS
+#include <tpm.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-#endif
 #include <cbfs.h>
 #include <ec/quanta/it8518/ec.h>
 #include "ec.h"
@@ -251,8 +249,8 @@ void main(unsigned long bist)
 	northbridge_romstage_finalize(boot_mode==2);
 
 	post_code(0x3f);
-#if CONFIG_CHROMEOS
+	if (CONFIG_LPC_TPM) {
-	init_chromeos(boot_mode);
+		init_tpm(boot_mode == 2);
-#endif
+	}
 	timestamp_add_now(TS_END_ROMSTAGE);
 }

src/mainboard/intel/baskingridge/Kconfig

@@ -11,6 +11,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_ACPI_RESUME
 	select HAVE_SMI_HANDLER
 	select MAINBOARD_HAS_CHROMEOS
+	select MAINBOARD_HAS_LPC_TPM
 	select INTEL_INT15
 	select CHROMEOS_VBNV_CMOS
 

src/mainboard/intel/emeraldlake2/romstage.c

@@ -39,10 +39,8 @@
 #include <cpu/x86/bist.h>
 #include <cpu/x86/msr.h>
 #include <halt.h>
+#include <tpm.h>
 #include "gpio.h"
-#if CONFIG_CHROMEOS
-#include <vendorcode/google/chromeos/chromeos.h>
-#endif
 
 #define SIO_PORT 0x164e
 
@@ -255,8 +253,8 @@ void main(unsigned long bist)
 	northbridge_romstage_finalize(boot_mode==2);
 
 	post_code(0x3f);
-#if CONFIG_CHROMEOS
+	if (CONFIG_LPC_TPM) {
-	init_chromeos(boot_mode);
+		init_tpm(boot_mode == 2);
-#endif
+	}
 	timestamp_add_now(TS_END_ROMSTAGE);
 }

src/mainboard/intel/wtm2/Kconfig

@@ -9,6 +9,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_ACPI_RESUME
 	select HAVE_SMI_HANDLER
 	select MAINBOARD_HAS_CHROMEOS
+	select MAINBOARD_HAS_LPC_TPM
 	select MAINBOARD_HAS_NATIVE_VGA_INIT
 	select INTEL_INT15
 

src/mainboard/samsung/lumpy/Kconfig

@@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select SYSTEM_TYPE_LAPTOP
 	select BOARD_ROMSIZE_KB_8192
 	select MAINBOARD_HAS_CHROMEOS
+	select MAINBOARD_HAS_LPC_TPM
 	select CPU_INTEL_SOCKET_RPGA989
 	select EC_SMSC_MEC1308
 	select HAVE_ACPI_RESUME

src/mainboard/samsung/lumpy/romstage.c

@@ -32,6 +32,7 @@
 #include <cbmem.h>
 #include <console/console.h>
 #include <bootmode.h>
+#include <tpm.h>
 #include <northbridge/intel/sandybridge/sandybridge.h>
 #include <northbridge/intel/sandybridge/raminit.h>
 #include <southbridge/intel/bd82x6x/pch.h>
@@ -45,9 +46,6 @@
 #if CONFIG_DRIVERS_UART_8250IO
 #include <superio/smsc/lpc47n207/lpc47n207.h>
 #endif
-#if CONFIG_CHROMEOS
-#include <vendorcode/google/chromeos/chromeos.h>
-#endif
 
 static void pch_enable_lpc(void)
 {
@@ -273,8 +271,8 @@ void main(unsigned long bist)
 	}
 	northbridge_romstage_finalize(boot_mode==2);
 	post_code(0x3f);
-#if CONFIG_CHROMEOS
+	if (CONFIG_LPC_TPM) {
-	init_chromeos(boot_mode);
+		init_tpm(boot_mode == 2);
-#endif
+	}
 	timestamp_add_now(TS_END_ROMSTAGE);
 }

src/mainboard/samsung/stumpy/Kconfig

@@ -4,6 +4,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select BOARD_ROMSIZE_KB_8192
 	select MAINBOARD_HAS_CHROMEOS
+	select MAINBOARD_HAS_LPC_TPM
 	select CPU_INTEL_SOCKET_RPGA989
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES

src/mainboard/samsung/stumpy/romstage.c

@@ -41,13 +41,11 @@
 #include <cpu/x86/bist.h>
 #include <cpu/x86/msr.h>
 #include <halt.h>
+#include <tpm.h>
 #include "gpio.h"
 #if CONFIG_DRIVERS_UART_8250IO
 #include <superio/smsc/lpc47n207/lpc47n207.h>
 #endif
-#if CONFIG_CHROMEOS
-#include <vendorcode/google/chromeos/chromeos.h>
-#endif
 
 /* Stumpy USB Reset Disable defined in cmos.layout */
 #if CONFIG_USE_OPTION_TABLE
@@ -283,8 +281,8 @@ void main(unsigned long bist)
 	northbridge_romstage_finalize(boot_mode==2);
 
 	post_code(0x3f);
-#if CONFIG_CHROMEOS
+	if (CONFIG_LPC_TPM) {
-	init_chromeos(boot_mode);
+		init_tpm(boot_mode == 2);
-#endif
+	}
 	timestamp_add_now(TS_END_ROMSTAGE);
 }

src/soc/intel/baytrail/romstage/romstage.c

@@ -33,6 +33,7 @@
 #include <romstage_handoff.h>
 #include <stage_cache.h>
 #include <timestamp.h>
+#include <tpm.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 #include <soc/gpio.h>
 #include <soc/iomap.h>
@@ -211,14 +212,6 @@ static int chipset_prev_sleep_state(struct chipset_power_state *ps)
 	return prev_sleep_state;
 }
 
-static inline void chromeos_init(int prev_sleep_state)
-{
-#if CONFIG_CHROMEOS
-	/* Normalize the sleep state to what init_chromeos() wants for S3: 2. */
-	init_chromeos(prev_sleep_state == 3 ? 2 : 0);
-#endif
-}
-
 /* Entry from the mainboard. */
 void romstage_common(struct romstage_params *params)
 {
@@ -250,7 +243,9 @@ void romstage_common(struct romstage_params *params)
 	else
 		printk(BIOS_DEBUG, "Romstage handoff structure not added!\n");
 
-	chromeos_init(prev_sleep_state);
+	if (CONFIG_LPC_TPM) {
+		init_tpm(prev_sleep_state == 3);
+	}
 }
 
 void asmlinkage romstage_after_car(void)

src/soc/intel/braswell/romstage/romstage.c

@@ -43,6 +43,7 @@
 #include <soc/romstage.h>
 #include <soc/smm.h>
 #include <soc/spi.h>
+#include <tpm.h>
 
 /* The cache-as-ram assembly file calls romstage_main() after setting up
  * cache-as-ram.  romstage_main() will then call the mainboards's
@@ -211,14 +212,6 @@ static int chipset_prev_sleep_state(struct chipset_power_state *ps)
 	return prev_sleep_state;
 }
 
-static inline void chromeos_init(int prev_sleep_state)
-{
-#if CONFIG_CHROMEOS
-	/* Normalize the sleep state to what init_chromeos() wants for S3: 2. */
-	init_chromeos(prev_sleep_state == 3 ? 2 : 0);
-#endif
-}
-
 /* Entry from the mainboard. */
 void romstage_common(struct romstage_params *params)
 {
@@ -250,7 +243,9 @@ void romstage_common(struct romstage_params *params)
 	else
 		printk(BIOS_DEBUG, "Romstage handoff structure not added!\n");
 
-	chromeos_init(prev_sleep_state);
+	if (CONFIG_LPC_TPM) {
+		init_tpm(prev_sleep_state == 3);
+	}
 }
 
 void asmlinkage romstage_after_car(void)

src/soc/intel/broadwell/romstage/romstage.c

@@ -29,6 +29,7 @@
 #include <cbmem.h>
 #include <cpu/x86/mtrr.h>
 #include <elog.h>
+#include <tpm.h>
 #include <romstage_handoff.h>
 #include <stage_cache.h>
 #include <timestamp.h>
@@ -89,14 +90,6 @@ void * asmlinkage romstage_main(unsigned long bist,
 	return setup_stack_and_mttrs();
 }
 
-static inline void chromeos_init(int prev_sleep_state)
-{
-#if CONFIG_CHROMEOS
-	/* Normalize the sleep state to what init_chromeos() wants for S3: 2 */
-	init_chromeos(prev_sleep_state == SLEEP_STATE_S3 ? 2 : 0);
-#endif
-}
-
 /* Entry from the mainboard. */
 void romstage_common(struct romstage_params *params)
 {
@@ -132,7 +125,9 @@ void romstage_common(struct romstage_params *params)
 	else
 		printk(BIOS_DEBUG, "Romstage handoff structure not added!\n");
 
-	chromeos_init(params->power_state->prev_sleep_state);
+#if CONFIG_LPC_TPM
+	init_tpm(prev_sleep_state == SLEEP_STATE_S3);
+#endif
 }
 
 void asmlinkage romstage_after_car(void)

src/vendorcode/google/chromeos/Kconfig

@@ -26,6 +26,8 @@ config CHROMEOS
 	bool "Build for ChromeOS"
 	default n
 	select TPM
+	select TPM_INIT_FAILURE_IS_FATAL
+	select SKIP_TPM_STARTUP_ON_NORMAL_BOOT
 	select BOOTMODE_STRAPS
 	select ELOG
 	help

src/vendorcode/google/chromeos/Makefile.inc

@@ -32,7 +32,6 @@ verstage-$(CONFIG_CHROMEOS_VBNV_FLASH) += vbnv_flash.c
 romstage-$(CONFIG_CHROMEOS_VBNV_FLASH) += vbnv_flash.c
 ramstage-$(CONFIG_CHROMEOS_VBNV_FLASH) += vbnv_flash.c
 
-romstage-$(CONFIG_ARCH_ROMSTAGE_X86_32) += vboot.c
 ramstage-$(CONFIG_ELOG) += elog.c
 ramstage-$(CONFIG_HAVE_ACPI_TABLES) += gnvs.c
 ramstage-$(CONFIG_CHROMEOS_RAMOOPS) += ramoops.c

src/vendorcode/google/chromeos/chromeos.h

@@ -39,9 +39,6 @@ void read_vbnv(uint8_t *vbnv_copy);
 void save_vbnv(const uint8_t *vbnv_copy);
 
 #if CONFIG_CHROMEOS
-/* functions implemented in vboot.c */
-void init_chromeos(int bootmode);
-
 /* functions implemented in elog.c */
 void elog_add_boot_reason(void);
 
@@ -53,7 +50,6 @@ int vboot_enable_developer(void);
 int vboot_enable_recovery(void);
 int vboot_skip_display_init(void);
 #else
-static inline void init_chromeos(int bootmode) { }
 static inline void elog_add_boot_reason(void) { return; }
 static inline void elog_add_watchdog_reset(void) { return; }
 static inline void reboot_from_watchdog(void) { return; }