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intel/fsp: Update Cannonlake FSP header 

Update Cannonlake FSP header to version 7.x.2E.50, the following changes
were made,
Memory Init UPD:
	1. Add GDXC configuration options.
	2. Remove some internal graphics memory selections.
	2. Remove Fixed mid option for SaGv.
	3. Add DualDimm per channel board type.
	4. Remove PEG IMR options.
Silicon Init UPD:
	1. Add CD clock selections of 675MHz.
	2. Remove Pcode PreWake/Rampup/RampDn time selections.
	3. Remove C3 state demotion/unDemotion selections.

BUG=None
TEST=Build and boot up on meowth platform.

Change-Id: I08ffb14df9f32089dbf44fa5bd3fc58a5bedb90d
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/26148
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Lijian Zhao 2018-05-07 16:40:41 -07:00 committed by Patrick Georgi
parent 65cbbe77ac
commit 0e9bbcc905
2 changed files with 92 additions and 60 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

59
src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h
View File

@ -182,9 +182,15 @@ typedef struct {
**/ **/
UINT8 ProbelessTrace; UINT8 ProbelessTrace;
/** Offset 0x00A3 /** Offset 0x00A3 - GDXC IOT SIZE
Size of IOT and MOT is in 8 MB chunks
**/ **/
UINT8 UnusedUpdSpace0[2]; UINT8 GdxcIotSize;
/** Offset 0x00A4 - GDXC MOT SIZE
Size of IOT and MOT is in 8 MB chunks
**/
UINT8 GdxcMotSize;
/** Offset 0x00A5 - Enable SMBus /** Offset 0x00A5 - Enable SMBus
Enable/disable SMBus controller. Enable/disable SMBus controller.
@ -244,9 +250,7 @@ typedef struct {
/** Offset 0x00B8 - Internal Graphics Pre-allocated Memory /** Offset 0x00B8 - Internal Graphics Pre-allocated Memory
Size of memory preallocated for internal graphics. Size of memory preallocated for internal graphics.
0x00:0MB, 0x01:32MB, 0x02:64MB, 0xF0:4MB, 0xF1:8MB, 0xF2:12MB, 0xF3:16MB, 0xF4:20MB, 0x00:0 MB, 0x01:32 MB, 0x02:64 MB
0xF5:24MB, 0xF6:28MB, 0xF7:32MB, 0xF8:36MB, 0xF9:40MB, 0xFA:44MB, 0xFB:48MB, 0xFC:52MB,
0xFD:56MB, 0xFE:60MB
**/ **/
UINT8 IgdDvmt50PreAlloc; UINT8 IgdDvmt50PreAlloc;
@ -272,14 +276,14 @@ typedef struct {
/** Offset 0x00BC - SA GV /** Offset 0x00BC - SA GV
System Agent dynamic frequency support and when enabled memory will be training System Agent dynamic frequency support and when enabled memory will be training
at two different frequencies. Only effects ULX/ULT CPUs. 0=Disabled, 1=FixedLow, at two different frequencies. Only effects ULX/ULT CPUs. 0=Disabled, 1=FixedLow,
2=FixedMid, 3=FixedHigh, and 4=Enabled. 2=FixedHigh, and 3=Enabled.
0:Disabled, 1:FixedLow, 2:FixedMid, 3:FixedHigh, 4:Enabled 0:Disabled, 1:FixedLow, 2:FixedHigh, 3:Enabled
**/ **/
UINT8 SaGv; UINT8 SaGv;
/** Offset 0x00BD /** Offset 0x00BD
**/ **/
UINT8 UnusedUpdSpace1; UINT8 UnusedUpdSpace0;
/** Offset 0x00BE - DDR Frequency Limit /** Offset 0x00BE - DDR Frequency Limit
Maximum Memory Frequency Selections in Mhz. Valid values should match the refclk, Maximum Memory Frequency Selections in Mhz. Valid values should match the refclk,
@ -329,7 +333,7 @@ typedef struct {
/** Offset 0x00C8 /** Offset 0x00C8
**/ **/
UINT8 UnusedUpdSpace2[16]; UINT8 UnusedUpdSpace1[16];
/** Offset 0x00D8 - SPD Profile Selected /** Offset 0x00D8 - SPD Profile Selected
Select DIMM timing profile. Options are 0=Default profile, 1=Custom profile, 2=XMP Select DIMM timing profile. Options are 0=Default profile, 1=Custom profile, 2=XMP
@ -488,7 +492,7 @@ typedef struct {
/** Offset 0x00F8 /** Offset 0x00F8
**/ **/
UINT8 UnusedUpdSpace3[4]; UINT8 UnusedUpdSpace2[4];
/** Offset 0x00FC - Enable Intel HD Audio (Azalia) /** Offset 0x00FC - Enable Intel HD Audio (Azalia)
0: Disable, 1: Enable (Default) Azalia controller 0: Disable, 1: Enable (Default) Azalia controller
@ -510,7 +514,7 @@ typedef struct {
/** Offset 0x00FF /** Offset 0x00FF
**/ **/
UINT8 UnusedUpdSpace4; UINT8 UnusedUpdSpace3;
/** Offset 0x0100 - HECI1 BAR address /** Offset 0x0100 - HECI1 BAR address
BAR address of HECI1 BAR address of HECI1
@ -681,7 +685,7 @@ typedef struct {
/** Offset 0x0125 /** Offset 0x0125
**/ **/
UINT8 UnusedUpdSpace5[3]; UINT8 UnusedUpdSpace4[3];
/** Offset 0x0128 - DMI Gen3 Root port preset values per lane /** Offset 0x0128 - DMI Gen3 Root port preset values per lane
Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane
@ -720,7 +724,7 @@ typedef struct {
/** Offset 0x0146 /** Offset 0x0146
**/ **/
UINT8 UnusedUpdSpace6[2]; UINT8 UnusedUpdSpace5[2];
/** Offset 0x0148 - PEG Gen3 RxCTLEp per-Bundle control /** Offset 0x0148 - PEG Gen3 RxCTLEp per-Bundle control
Range: 0-15, 12 is default for each bundle, must be specified based upon platform design Range: 0-15, 12 is default for each bundle, must be specified based upon platform design
@ -957,7 +961,7 @@ typedef struct {
/** Offset 0x0207 /** Offset 0x0207
**/ **/
UINT8 UnusedUpdSpace7; UINT8 UnusedUpdSpace6;
/** Offset 0x0208 - Maximum clr turbo ratio override /** Offset 0x0208 - Maximum clr turbo ratio override
Maximum clr turbo ratio override allows to increase CPU clr frequency beyond the Maximum clr turbo ratio override allows to increase CPU clr frequency beyond the
@ -2275,21 +2279,18 @@ typedef struct {
**/ **/
UINT8 EnBER; UINT8 EnBER;
/** Offset 0x050F - PEG IMR support /** Offset 0x050F - Dual Dimm Per-Channel Board Type
This option configures the IMR support for PEG.(def=Disable) Option to indicate if Board Layout includes One/Two DIMMs per channel. This is used
to limit maximum frequency for some SKUs.
0:1DPC, 1:2DPC
**/
UINT8 DualDimmPerChannelBoardType;
/** Offset 0x0510 - CFL Reserved
Reserved FspmConfig CFL
$EN_DIS $EN_DIS
**/ **/
UINT8 PegImrEnable; UINT8 ReservedFspmUpdCfl[3];
/** Offset 0x0510 - PEG IMR size
The size of IMR to be allocated for PEG EndPoint device
**/
UINT16 PegImrSize;
/** Offset 0x0512 - PEG Root Port Selection
The Root Port for which the IMR to be allocated
**/
UINT8 PegImrRpSelection;
/** Offset 0x0513 - Memory Test on Warm Boot /** Offset 0x0513 - Memory Test on Warm Boot
Run Base Memory Test on Warm Boot Run Base Memory Test on Warm Boot
@ -2524,7 +2525,7 @@ typedef struct {
/** Offset 0x0579 /** Offset 0x0579
**/ **/
UINT8 UnusedUpdSpace10; UINT8 UnusedUpdSpace9;
/** Offset 0x057A - Jitter Dwell Time for PCIe Gen3 Software Equalization /** Offset 0x057A - Jitter Dwell Time for PCIe Gen3 Software Equalization
Range: 0-65535, default is 1000. @warning Do not change from the default Range: 0-65535, default is 1000. @warning Do not change from the default
@ -2799,7 +2800,7 @@ typedef struct {
/** Offset 0x051F /** Offset 0x051F
**/ **/
UINT8 UnusedUpdSpace9; UINT8 UnusedUpdSpace8;
/** Offset 0x0520 /** Offset 0x0520
**/ **/

93
src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h
View File

@ -717,8 +717,8 @@ typedef struct {
UINT8 PavpEnable; UINT8 PavpEnable;
/** Offset 0x0217 - CdClock Frequency selection /** Offset 0x0217 - CdClock Frequency selection
0=168 Mhz, 1=336 Mhz, 2(Default)=528 Mhz 0=168 Mhz, 1=336 Mhz, 2=528 Mhz, 3(Default)=675 Mhz
0: 168 Mhz, 1: 336 Mhz, 2: 528 Mhz 0: 168 Mhz, 1: 336 Mhz, 2: 528 Mhz, 3: 675 Mhz
**/ **/
UINT8 CdClock; UINT8 CdClock;
@ -907,7 +907,9 @@ typedef struct {
UINT8 PsysOffset; UINT8 PsysOffset;
/** Offset 0x02A2 - Acoustic Noise Mitigation feature /** Offset 0x02A2 - Acoustic Noise Mitigation feature
Enable or Disable Acoustic Noise Mitigation feature. <b>0: Disabled</b>; 1: Enabled Enable or Disable Acoustic Noise Mitigation feature. This has to be enabled to program
slew rate configuration for all VR domains, Pre Wake, Ramp Up and, Ramp Down times.<b>0:
Disabled</b>; 1: Enabled
$EN_DIS $EN_DIS
**/ **/
UINT8 AcousticNoiseMitigation; UINT8 AcousticNoiseMitigation;
@ -1100,15 +1102,32 @@ typedef struct {
**/ **/
UINT32 VrPowerDeliveryDesign; UINT32 VrPowerDeliveryDesign;
/** Offset 0x0328 - ReservedCpuPostMemProduction /** Offset 0x0328 - Pre Wake Randomization time
PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum pre-wake randomization
time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled.
Range 0-255 <b>0</b>.
**/
UINT8 PreWake;
/** Offset 0x0329 - Ramp Up Randomization time
PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum Ramp Up randomization
time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled.Range
0-255 <b>0</b>.
**/
UINT8 RampUp;
/** Offset 0x032A - Ramp Down Randomization time
PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum Ramp Down randomization
time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled.Range
0-255 <b>0</b>.
**/
UINT8 RampDown;
/** Offset 0x032B - ReservedCpuPostMemProduction
Reserved for CPU Post-Mem Production Reserved for CPU Post-Mem Production
$EN_DIS $EN_DIS
**/ **/
UINT8 ReservedCpuPostMemProduction[1]; UINT8 ReservedCpuPostMemProduction[27];
/** Offset 0x0329
**/
UINT8 UnusedUpdSpace10[29];
/** Offset 0x0346 - Enable DMI ASPM /** Offset 0x0346 - Enable DMI ASPM
Deprecated. Deprecated.
@ -1151,7 +1170,7 @@ typedef struct {
/** Offset 0x0367 /** Offset 0x0367
**/ **/
UINT8 UnusedUpdSpace11; UINT8 UnusedUpdSpace10;
/** Offset 0x0368 - VC Type /** Offset 0x0368 - VC Type
Virtual Channel Type Select: 0: VC0, 1: VC1. Virtual Channel Type Select: 0: VC0, 1: VC1.
@ -1192,7 +1211,7 @@ typedef struct {
/** Offset 0x036E /** Offset 0x036E
**/ **/
UINT8 UnusedUpdSpace12[15]; UINT8 UnusedUpdSpace11[15];
/** Offset 0x037D - Enable PCH Io Apic Entry 24-119 /** Offset 0x037D - Enable PCH Io Apic Entry 24-119
0: Disable; 1: Enable. 0: Disable; 1: Enable.
@ -1207,7 +1226,7 @@ typedef struct {
/** Offset 0x037F /** Offset 0x037F
**/ **/
UINT8 UnusedUpdSpace13; UINT8 UnusedUpdSpace12;
/** Offset 0x0380 - Enable PCH ISH SPI GPIO pins assigned /** Offset 0x0380 - Enable PCH ISH SPI GPIO pins assigned
0: Disable; 1: Enable. 0: Disable; 1: Enable.
@ -1307,7 +1326,7 @@ typedef struct {
/** Offset 0x0390 /** Offset 0x0390
**/ **/
UINT8 UnusedUpdSpace14[3]; UINT8 UnusedUpdSpace13[3];
/** Offset 0x0393 - Enable LOCKDOWN BIOS LOCK /** Offset 0x0393 - Enable LOCKDOWN BIOS LOCK
Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region
@ -1401,7 +1420,7 @@ typedef struct {
/** Offset 0x04E6 /** Offset 0x04E6
**/ **/
UINT8 UnusedUpdSpace15[24]; UINT8 UnusedUpdSpace14[24];
/** Offset 0x04FE - PCIE RP Pcie Speed /** Offset 0x04FE - PCIE RP Pcie Speed
Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see: Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see:
@ -1427,7 +1446,7 @@ typedef struct {
/** Offset 0x055E /** Offset 0x055E
**/ **/
UINT8 UnusedUpdSpace16[106]; UINT8 UnusedUpdSpace15[106];
/** Offset 0x05C8 - PCIE RP Aspm /** Offset 0x05C8 - PCIE RP Aspm
The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is
@ -1486,7 +1505,7 @@ typedef struct {
/** Offset 0x0664 /** Offset 0x0664
**/ **/
UINT8 UnusedUpdSpace17; UINT8 UnusedUpdSpace16;
/** Offset 0x0665 - PCIE Compliance Test Mode /** Offset 0x0665 - PCIE Compliance Test Mode
Compliance Test Mode shall be enabled when using Compliance Load Board. Compliance Test Mode shall be enabled when using Compliance Load Board.
@ -1503,7 +1522,7 @@ typedef struct {
/** Offset 0x0667 /** Offset 0x0667
**/ **/
UINT8 UnusedUpdSpace18[2]; UINT8 UnusedUpdSpace17[2];
/** Offset 0x0669 - PCH Pm PME_B0_S5_DIS /** Offset 0x0669 - PCH Pm PME_B0_S5_DIS
When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1. When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1.
@ -1529,7 +1548,7 @@ typedef struct {
/** Offset 0x066F /** Offset 0x066F
**/ **/
UINT8 UnusedUpdSpace19; UINT8 UnusedUpdSpace18;
/** Offset 0x0670 - PCH Pm Wol Enable Override /** Offset 0x0670 - PCH Pm Wol Enable Override
Corresponds to the WOL Enable Override bit in the General PM Configuration B (GEN_PMCON_B) register. Corresponds to the WOL Enable Override bit in the General PM Configuration B (GEN_PMCON_B) register.
@ -1618,7 +1637,7 @@ typedef struct {
/** Offset 0x067D /** Offset 0x067D
**/ **/
UINT8 UnusedUpdSpace20[3]; UINT8 UnusedUpdSpace19[3];
/** Offset 0x0680 - PCH Pm Lpc Clock Run /** Offset 0x0680 - PCH Pm Lpc Clock Run
This member describes whether or not the LPC ClockRun feature of PCH should be enabled. This member describes whether or not the LPC ClockRun feature of PCH should be enabled.
@ -1652,7 +1671,7 @@ typedef struct {
/** Offset 0x0685 /** Offset 0x0685
**/ **/
UINT8 UnusedUpdSpace21; UINT8 UnusedUpdSpace20;
/** Offset 0x0686 - PCH Pm Disable Native Power Button /** Offset 0x0686 - PCH Pm Disable Native Power Button
Power button native mode disable. Power button native mode disable.
@ -1692,7 +1711,7 @@ typedef struct {
/** Offset 0x068C /** Offset 0x068C
**/ **/
UINT8 UnusedUpdSpace22; UINT8 UnusedUpdSpace21;
/** Offset 0x068D - PCH Sata Pwr Opt Enable /** Offset 0x068D - PCH Sata Pwr Opt Enable
SATA Power Optimizer on PCH side. SATA Power Optimizer on PCH side.
@ -1881,7 +1900,7 @@ typedef struct {
/** Offset 0x0700 /** Offset 0x0700
**/ **/
UINT8 UnusedUpdSpace23; UINT8 UnusedUpdSpace22;
/** Offset 0x0701 - PcdSerialIoUart0PinMuxing /** Offset 0x0701 - PcdSerialIoUart0PinMuxing
Select SerialIo Uart0 pin muxing. Setting applicable only if SerialIO UART0 is enabled. Select SerialIo Uart0 pin muxing. Setting applicable only if SerialIO UART0 is enabled.
@ -1891,7 +1910,7 @@ typedef struct {
/** Offset 0x0702 /** Offset 0x0702
**/ **/
UINT8 UnusedUpdSpace24[1]; UINT8 UnusedUpdSpace23[1];
/** Offset 0x0703 - Enables UART hardware flow control, CTS and RTS lines /** Offset 0x0703 - Enables UART hardware flow control, CTS and RTS lines
Enables UART hardware flow control, CTS and RTS linesh. Enables UART hardware flow control, CTS and RTS linesh.
@ -2164,7 +2183,7 @@ typedef struct {
/** Offset 0x0753 /** Offset 0x0753
**/ **/
UINT8 UnusedUpdSpace25; UINT8 UnusedUpdSpace24;
/** Offset 0x0754 - Pch PCIE device override table pointer /** Offset 0x0754 - Pch PCIE device override table pointer
The PCIe device table is being used to override PCIe device ASPM settings. This The PCIe device table is being used to override PCIe device ASPM settings. This
@ -2343,7 +2362,7 @@ typedef struct {
UINT8 PmSupport; UINT8 PmSupport;
/** Offset 0x07BC - Enable/Disable CdynmaxClamp /** Offset 0x07BC - Enable/Disable CdynmaxClamp
Enable: Enable CdynmaxClamp, Disable(Default): Disable CdynmaxClamp Enable(Default): Enable CdynmaxClamp, Disable: Disable CdynmaxClamp
$EN_DIS $EN_DIS
**/ **/
UINT8 CdynmaxClampEnable; UINT8 CdynmaxClampEnable;
@ -2465,7 +2484,7 @@ typedef struct {
/** Offset 0x07D8 - TCC Activation Offset /** Offset 0x07D8 - TCC Activation Offset
TCC Activation Offset. Offset from factory set TCC activation temperature at which TCC Activation Offset. Offset from factory set TCC activation temperature at which
the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation
Temperature, in volts.For Y SKU, the recommended default for this policy is <b>10</b>, Temperature, in volts.For Y SKU, the recommended default for this policy is <b>15</b>,
For all other SKUs the recommended default are <b>0</b> For all other SKUs the recommended default are <b>0</b>
**/ **/
UINT8 TccActivationOffset; UINT8 TccActivationOffset;
@ -2792,8 +2811,8 @@ typedef struct {
UINT8 CstateLatencyControl5TimeUnit; UINT8 CstateLatencyControl5TimeUnit;
/** Offset 0x0819 - Interrupt Redirection Mode Select /** Offset 0x0819 - Interrupt Redirection Mode Select
Interrupt Redirection Mode Select.0: Fixed priority; 1: Round robin;2: Hash vector;7: Interrupt Redirection Mode Select.0: Fixed priority; 1: Round robin;2: Hash vector;4:
No change. PAIR with fixed priority;5: PAIR with round robin;6: PAIR with hash vector;7: No change.
**/ **/
UINT8 PpmIrmSetting; UINT8 PpmIrmSetting;
@ -3040,11 +3059,23 @@ typedef struct {
**/ **/
UINT8 MaxRingRatioLimit; UINT8 MaxRingRatioLimit;
/** Offset 0x08A5 - ReservedCpuPostMemTest /** Offset 0x08A5 - Enable or Disable C3 Cstate Demotion
Enable or Disable C3 Cstate Demotion. Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 C3StateAutoDemotion;
/** Offset 0x08A6 - Enable or Disable C3 Cstate UnDemotion
Enable or Disable C3 Cstate UnDemotion. Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 C3StateUnDemotion;
/** Offset 0x08A7 - ReservedCpuPostMemTest
Reserved for CPU Post-Mem Test Reserved for CPU Post-Mem Test
$EN_DIS $EN_DIS
**/ **/
UINT8 ReservedCpuPostMemTest[21]; UINT8 ReservedCpuPostMemTest[19];
/** Offset 0x08BA - SgxSinitDataFromTpm /** Offset 0x08BA - SgxSinitDataFromTpm
SgxSinitDataFromTpm default values SgxSinitDataFromTpm default values
@ -3194,7 +3225,7 @@ typedef struct {
/** Offset 0x0A61 /** Offset 0x0A61
**/ **/
UINT8 UnusedUpdSpace26[17]; UINT8 UnusedUpdSpace25[17];
/** Offset 0x0A72 - Skip POSTBOOT SAI /** Offset 0x0A72 - Skip POSTBOOT SAI
Deprecated Deprecated