intel/fsp: Update Cannonlake FSP header
Update Cannonlake FSP header to version 7.x.2E.50, the following changes were made, Memory Init UPD: 1. Add GDXC configuration options. 2. Remove some internal graphics memory selections. 2. Remove Fixed mid option for SaGv. 3. Add DualDimm per channel board type. 4. Remove PEG IMR options. Silicon Init UPD: 1. Add CD clock selections of 675MHz. 2. Remove Pcode PreWake/Rampup/RampDn time selections. 3. Remove C3 state demotion/unDemotion selections. BUG=None TEST=Build and boot up on meowth platform. Change-Id: I08ffb14df9f32089dbf44fa5bd3fc58a5bedb90d Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/26148 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Lijian Zhao
Patrick Georgi
parent
65cbbe77ac
commit
0e9bbcc905
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@ -182,9 +182,15 @@ typedef struct {
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**/
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UINT8 ProbelessTrace;
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/** Offset 0x00A3
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/** Offset 0x00A3 - GDXC IOT SIZE
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Size of IOT and MOT is in 8 MB chunks
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**/
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UINT8 UnusedUpdSpace0[2];
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UINT8 GdxcIotSize;
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/** Offset 0x00A4 - GDXC MOT SIZE
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Size of IOT and MOT is in 8 MB chunks
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**/
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UINT8 GdxcMotSize;
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/** Offset 0x00A5 - Enable SMBus
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Enable/disable SMBus controller.
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@ -244,9 +250,7 @@ typedef struct {
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/** Offset 0x00B8 - Internal Graphics Pre-allocated Memory
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Size of memory preallocated for internal graphics.
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0x00:0MB, 0x01:32MB, 0x02:64MB, 0xF0:4MB, 0xF1:8MB, 0xF2:12MB, 0xF3:16MB, 0xF4:20MB,
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0xF5:24MB, 0xF6:28MB, 0xF7:32MB, 0xF8:36MB, 0xF9:40MB, 0xFA:44MB, 0xFB:48MB, 0xFC:52MB,
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0xFD:56MB, 0xFE:60MB
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0x00:0 MB, 0x01:32 MB, 0x02:64 MB
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**/
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UINT8 IgdDvmt50PreAlloc;
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@ -272,14 +276,14 @@ typedef struct {
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/** Offset 0x00BC - SA GV
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System Agent dynamic frequency support and when enabled memory will be training
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at two different frequencies. Only effects ULX/ULT CPUs. 0=Disabled, 1=FixedLow,
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2=FixedMid, 3=FixedHigh, and 4=Enabled.
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0:Disabled, 1:FixedLow, 2:FixedMid, 3:FixedHigh, 4:Enabled
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2=FixedHigh, and 3=Enabled.
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0:Disabled, 1:FixedLow, 2:FixedHigh, 3:Enabled
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**/
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UINT8 SaGv;
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/** Offset 0x00BD
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**/
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UINT8 UnusedUpdSpace1;
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UINT8 UnusedUpdSpace0;
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/** Offset 0x00BE - DDR Frequency Limit
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Maximum Memory Frequency Selections in Mhz. Valid values should match the refclk,
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@ -329,7 +333,7 @@ typedef struct {
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/** Offset 0x00C8
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**/
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UINT8 UnusedUpdSpace2[16];
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UINT8 UnusedUpdSpace1[16];
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/** Offset 0x00D8 - SPD Profile Selected
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Select DIMM timing profile. Options are 0=Default profile, 1=Custom profile, 2=XMP
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@ -488,7 +492,7 @@ typedef struct {
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/** Offset 0x00F8
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**/
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UINT8 UnusedUpdSpace3[4];
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UINT8 UnusedUpdSpace2[4];
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/** Offset 0x00FC - Enable Intel HD Audio (Azalia)
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0: Disable, 1: Enable (Default) Azalia controller
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@ -510,7 +514,7 @@ typedef struct {
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/** Offset 0x00FF
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**/
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UINT8 UnusedUpdSpace4;
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UINT8 UnusedUpdSpace3;
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/** Offset 0x0100 - HECI1 BAR address
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BAR address of HECI1
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@ -681,7 +685,7 @@ typedef struct {
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/** Offset 0x0125
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**/
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UINT8 UnusedUpdSpace5[3];
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UINT8 UnusedUpdSpace4[3];
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/** Offset 0x0128 - DMI Gen3 Root port preset values per lane
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Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane
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@ -720,7 +724,7 @@ typedef struct {
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/** Offset 0x0146
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**/
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UINT8 UnusedUpdSpace6[2];
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UINT8 UnusedUpdSpace5[2];
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/** Offset 0x0148 - PEG Gen3 RxCTLEp per-Bundle control
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Range: 0-15, 12 is default for each bundle, must be specified based upon platform design
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@ -957,7 +961,7 @@ typedef struct {
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/** Offset 0x0207
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**/
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UINT8 UnusedUpdSpace7;
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UINT8 UnusedUpdSpace6;
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/** Offset 0x0208 - Maximum clr turbo ratio override
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Maximum clr turbo ratio override allows to increase CPU clr frequency beyond the
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@ -2275,21 +2279,18 @@ typedef struct {
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**/
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UINT8 EnBER;
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/** Offset 0x050F - PEG IMR support
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This option configures the IMR support for PEG.(def=Disable)
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/** Offset 0x050F - Dual Dimm Per-Channel Board Type
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Option to indicate if Board Layout includes One/Two DIMMs per channel. This is used
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to limit maximum frequency for some SKUs.
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0:1DPC, 1:2DPC
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**/
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UINT8 DualDimmPerChannelBoardType;
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/** Offset 0x0510 - CFL Reserved
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Reserved FspmConfig CFL
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$EN_DIS
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**/
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UINT8 PegImrEnable;
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/** Offset 0x0510 - PEG IMR size
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The size of IMR to be allocated for PEG EndPoint device
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**/
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UINT16 PegImrSize;
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/** Offset 0x0512 - PEG Root Port Selection
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The Root Port for which the IMR to be allocated
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**/
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UINT8 PegImrRpSelection;
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UINT8 ReservedFspmUpdCfl[3];
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/** Offset 0x0513 - Memory Test on Warm Boot
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Run Base Memory Test on Warm Boot
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@ -2524,7 +2525,7 @@ typedef struct {
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/** Offset 0x0579
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**/
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UINT8 UnusedUpdSpace10;
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UINT8 UnusedUpdSpace9;
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/** Offset 0x057A - Jitter Dwell Time for PCIe Gen3 Software Equalization
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Range: 0-65535, default is 1000. @warning Do not change from the default
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@ -2799,7 +2800,7 @@ typedef struct {
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/** Offset 0x051F
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**/
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UINT8 UnusedUpdSpace9;
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UINT8 UnusedUpdSpace8;
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/** Offset 0x0520
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**/
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@ -717,8 +717,8 @@ typedef struct {
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UINT8 PavpEnable;
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/** Offset 0x0217 - CdClock Frequency selection
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0=168 Mhz, 1=336 Mhz, 2(Default)=528 Mhz
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0: 168 Mhz, 1: 336 Mhz, 2: 528 Mhz
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0=168 Mhz, 1=336 Mhz, 2=528 Mhz, 3(Default)=675 Mhz
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0: 168 Mhz, 1: 336 Mhz, 2: 528 Mhz, 3: 675 Mhz
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**/
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UINT8 CdClock;
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@ -907,7 +907,9 @@ typedef struct {
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UINT8 PsysOffset;
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/** Offset 0x02A2 - Acoustic Noise Mitigation feature
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Enable or Disable Acoustic Noise Mitigation feature. <b>0: Disabled</b>; 1: Enabled
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Enable or Disable Acoustic Noise Mitigation feature. This has to be enabled to program
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slew rate configuration for all VR domains, Pre Wake, Ramp Up and, Ramp Down times.<b>0:
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Disabled</b>; 1: Enabled
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$EN_DIS
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**/
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UINT8 AcousticNoiseMitigation;
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@ -1100,15 +1102,32 @@ typedef struct {
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**/
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UINT32 VrPowerDeliveryDesign;
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/** Offset 0x0328 - ReservedCpuPostMemProduction
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/** Offset 0x0328 - Pre Wake Randomization time
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PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum pre-wake randomization
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time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled.
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Range 0-255 <b>0</b>.
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**/
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UINT8 PreWake;
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/** Offset 0x0329 - Ramp Up Randomization time
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PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum Ramp Up randomization
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time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled.Range
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0-255 <b>0</b>.
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**/
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UINT8 RampUp;
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/** Offset 0x032A - Ramp Down Randomization time
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PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum Ramp Down randomization
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time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled.Range
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0-255 <b>0</b>.
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**/
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UINT8 RampDown;
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/** Offset 0x032B - ReservedCpuPostMemProduction
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Reserved for CPU Post-Mem Production
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$EN_DIS
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**/
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UINT8 ReservedCpuPostMemProduction[1];
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/** Offset 0x0329
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**/
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UINT8 UnusedUpdSpace10[29];
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UINT8 ReservedCpuPostMemProduction[27];
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/** Offset 0x0346 - Enable DMI ASPM
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Deprecated.
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@ -1151,7 +1170,7 @@ typedef struct {
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/** Offset 0x0367
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**/
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UINT8 UnusedUpdSpace11;
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UINT8 UnusedUpdSpace10;
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/** Offset 0x0368 - VC Type
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Virtual Channel Type Select: 0: VC0, 1: VC1.
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@ -1192,7 +1211,7 @@ typedef struct {
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/** Offset 0x036E
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**/
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UINT8 UnusedUpdSpace12[15];
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UINT8 UnusedUpdSpace11[15];
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/** Offset 0x037D - Enable PCH Io Apic Entry 24-119
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0: Disable; 1: Enable.
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@ -1207,7 +1226,7 @@ typedef struct {
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/** Offset 0x037F
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**/
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UINT8 UnusedUpdSpace13;
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UINT8 UnusedUpdSpace12;
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/** Offset 0x0380 - Enable PCH ISH SPI GPIO pins assigned
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0: Disable; 1: Enable.
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@ -1307,7 +1326,7 @@ typedef struct {
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/** Offset 0x0390
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**/
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UINT8 UnusedUpdSpace14[3];
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UINT8 UnusedUpdSpace13[3];
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/** Offset 0x0393 - Enable LOCKDOWN BIOS LOCK
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Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region
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@ -1401,7 +1420,7 @@ typedef struct {
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/** Offset 0x04E6
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**/
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UINT8 UnusedUpdSpace15[24];
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UINT8 UnusedUpdSpace14[24];
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/** Offset 0x04FE - PCIE RP Pcie Speed
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Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see:
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@ -1427,7 +1446,7 @@ typedef struct {
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/** Offset 0x055E
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**/
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UINT8 UnusedUpdSpace16[106];
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UINT8 UnusedUpdSpace15[106];
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/** Offset 0x05C8 - PCIE RP Aspm
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The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is
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@ -1486,7 +1505,7 @@ typedef struct {
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/** Offset 0x0664
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**/
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UINT8 UnusedUpdSpace17;
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UINT8 UnusedUpdSpace16;
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/** Offset 0x0665 - PCIE Compliance Test Mode
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Compliance Test Mode shall be enabled when using Compliance Load Board.
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@ -1503,7 +1522,7 @@ typedef struct {
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/** Offset 0x0667
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**/
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UINT8 UnusedUpdSpace18[2];
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UINT8 UnusedUpdSpace17[2];
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/** Offset 0x0669 - PCH Pm PME_B0_S5_DIS
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When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1.
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@ -1529,7 +1548,7 @@ typedef struct {
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/** Offset 0x066F
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**/
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UINT8 UnusedUpdSpace19;
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UINT8 UnusedUpdSpace18;
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/** Offset 0x0670 - PCH Pm Wol Enable Override
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Corresponds to the WOL Enable Override bit in the General PM Configuration B (GEN_PMCON_B) register.
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@ -1618,7 +1637,7 @@ typedef struct {
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/** Offset 0x067D
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**/
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UINT8 UnusedUpdSpace20[3];
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UINT8 UnusedUpdSpace19[3];
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/** Offset 0x0680 - PCH Pm Lpc Clock Run
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This member describes whether or not the LPC ClockRun feature of PCH should be enabled.
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@ -1652,7 +1671,7 @@ typedef struct {
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/** Offset 0x0685
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**/
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UINT8 UnusedUpdSpace21;
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UINT8 UnusedUpdSpace20;
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/** Offset 0x0686 - PCH Pm Disable Native Power Button
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Power button native mode disable.
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@ -1692,7 +1711,7 @@ typedef struct {
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/** Offset 0x068C
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**/
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UINT8 UnusedUpdSpace22;
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UINT8 UnusedUpdSpace21;
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/** Offset 0x068D - PCH Sata Pwr Opt Enable
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SATA Power Optimizer on PCH side.
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@ -1881,7 +1900,7 @@ typedef struct {
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/** Offset 0x0700
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**/
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UINT8 UnusedUpdSpace23;
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UINT8 UnusedUpdSpace22;
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/** Offset 0x0701 - PcdSerialIoUart0PinMuxing
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Select SerialIo Uart0 pin muxing. Setting applicable only if SerialIO UART0 is enabled.
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@ -1891,7 +1910,7 @@ typedef struct {
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/** Offset 0x0702
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**/
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UINT8 UnusedUpdSpace24[1];
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UINT8 UnusedUpdSpace23[1];
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/** Offset 0x0703 - Enables UART hardware flow control, CTS and RTS lines
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Enables UART hardware flow control, CTS and RTS linesh.
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@ -2164,7 +2183,7 @@ typedef struct {
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/** Offset 0x0753
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**/
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UINT8 UnusedUpdSpace25;
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UINT8 UnusedUpdSpace24;
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/** Offset 0x0754 - Pch PCIE device override table pointer
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The PCIe device table is being used to override PCIe device ASPM settings. This
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@ -2343,7 +2362,7 @@ typedef struct {
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UINT8 PmSupport;
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/** Offset 0x07BC - Enable/Disable CdynmaxClamp
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Enable: Enable CdynmaxClamp, Disable(Default): Disable CdynmaxClamp
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Enable(Default): Enable CdynmaxClamp, Disable: Disable CdynmaxClamp
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$EN_DIS
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**/
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UINT8 CdynmaxClampEnable;
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@ -2465,7 +2484,7 @@ typedef struct {
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/** Offset 0x07D8 - TCC Activation Offset
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TCC Activation Offset. Offset from factory set TCC activation temperature at which
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the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation
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Temperature, in volts.For Y SKU, the recommended default for this policy is <b>10</b>,
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Temperature, in volts.For Y SKU, the recommended default for this policy is <b>15</b>,
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For all other SKUs the recommended default are <b>0</b>
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**/
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UINT8 TccActivationOffset;
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@ -2792,8 +2811,8 @@ typedef struct {
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UINT8 CstateLatencyControl5TimeUnit;
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/** Offset 0x0819 - Interrupt Redirection Mode Select
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Interrupt Redirection Mode Select.0: Fixed priority; 1: Round robin;2: Hash vector;7:
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No change.
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Interrupt Redirection Mode Select.0: Fixed priority; 1: Round robin;2: Hash vector;4:
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PAIR with fixed priority;5: PAIR with round robin;6: PAIR with hash vector;7: No change.
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**/
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UINT8 PpmIrmSetting;
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@ -3040,11 +3059,23 @@ typedef struct {
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**/
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UINT8 MaxRingRatioLimit;
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/** Offset 0x08A5 - ReservedCpuPostMemTest
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/** Offset 0x08A5 - Enable or Disable C3 Cstate Demotion
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Enable or Disable C3 Cstate Demotion. Disable; <b>1: Enable</b>
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$EN_DIS
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**/
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UINT8 C3StateAutoDemotion;
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/** Offset 0x08A6 - Enable or Disable C3 Cstate UnDemotion
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Enable or Disable C3 Cstate UnDemotion. Disable; <b>1: Enable</b>
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$EN_DIS
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**/
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UINT8 C3StateUnDemotion;
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/** Offset 0x08A7 - ReservedCpuPostMemTest
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Reserved for CPU Post-Mem Test
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$EN_DIS
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**/
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UINT8 ReservedCpuPostMemTest[21];
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UINT8 ReservedCpuPostMemTest[19];
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/** Offset 0x08BA - SgxSinitDataFromTpm
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SgxSinitDataFromTpm default values
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@ -3194,7 +3225,7 @@ typedef struct {
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/** Offset 0x0A61
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**/
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UINT8 UnusedUpdSpace26[17];
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UINT8 UnusedUpdSpace25[17];
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/** Offset 0x0A72 - Skip POSTBOOT SAI
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Deprecated
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