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soc/amd/glinda,mendocino,phoenix/espi_util: add comment about register 

Even though the register name begins with ESPI, it resides in the SPI
registers and not in the eSPI registers, so add a comment to point this
out to hopefully avoid some confusion.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9f8d15ceb98f51aad0816021f98ec5c78953e7f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
This commit is contained in:
Felix Held 2023-01-19 23:06:54 +01:00
parent b85fd1e84f
commit 0e9dbf0843
3 changed files with 3 additions and 3 deletions
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2
src/soc/amd/glinda/espi_util.c
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@ -4,7 +4,7 @@
#include <soc/espi.h> #include <soc/espi.h>
#include <types.h> #include <types.h>
#define ESPI_CNTRL_REGISTER 0x10 #define ESPI_CNTRL_REGISTER 0x10 /* SPI register, not eSPI register! */
#define LOCK_SPIX10_BIT2 BIT(3) #define LOCK_SPIX10_BIT2 BIT(3)
#define ESPI_MUX_SPI1 BIT(2) #define ESPI_MUX_SPI1 BIT(2)
#define ROM_ADDR_WR_PROT BIT(1) #define ROM_ADDR_WR_PROT BIT(1)

2
src/soc/amd/mendocino/espi_util.c
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@ -4,7 +4,7 @@
#include <soc/espi.h> #include <soc/espi.h>
#include <types.h> #include <types.h>
#define ESPI_CNTRL_REGISTER 0x10 #define ESPI_CNTRL_REGISTER 0x10 /* SPI register, not eSPI register! */
#define LOCK_SPIX10_BIT2 BIT(3) #define LOCK_SPIX10_BIT2 BIT(3)
#define ESPI_MUX_SPI1 BIT(2) #define ESPI_MUX_SPI1 BIT(2)
#define ROM_ADDR_WR_PROT BIT(1) #define ROM_ADDR_WR_PROT BIT(1)

2
src/soc/amd/phoenix/espi_util.c
View File

@ -4,7 +4,7 @@
#include <soc/espi.h> #include <soc/espi.h>
#include <types.h> #include <types.h>
#define ESPI_CNTRL_REGISTER 0x10 #define ESPI_CNTRL_REGISTER 0x10 /* SPI register, not eSPI register! */
#define LOCK_SPIX10_BIT2 BIT(3) #define LOCK_SPIX10_BIT2 BIT(3)
#define ESPI_MUX_SPI1 BIT(2) #define ESPI_MUX_SPI1 BIT(2)
#define ROM_ADDR_WR_PROT BIT(1) #define ROM_ADDR_WR_PROT BIT(1)