soc/amd/glinda,mendocino,phoenix/espi_util: add comment about register

Even though the register name begins with ESPI, it resides in the SPI
registers and not in the eSPI registers, so add a comment to point this
out to hopefully avoid some confusion.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9f8d15ceb98f51aad0816021f98ec5c78953e7f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>

src/soc/amd/glinda/espi_util.c

@@ -4,7 +4,7 @@
 #include <soc/espi.h>
 #include <types.h>
 
-#define ESPI_CNTRL_REGISTER	0x10
+#define ESPI_CNTRL_REGISTER	0x10 /* SPI register, not eSPI register! */
 #define  LOCK_SPIX10_BIT2	BIT(3)
 #define  ESPI_MUX_SPI1		BIT(2)
 #define  ROM_ADDR_WR_PROT	BIT(1)

src/soc/amd/mendocino/espi_util.c

@@ -4,7 +4,7 @@
 #include <soc/espi.h>
 #include <types.h>
 
-#define ESPI_CNTRL_REGISTER	0x10
+#define ESPI_CNTRL_REGISTER	0x10 /* SPI register, not eSPI register! */
 #define  LOCK_SPIX10_BIT2	BIT(3)
 #define  ESPI_MUX_SPI1		BIT(2)
 #define  ROM_ADDR_WR_PROT	BIT(1)

src/soc/amd/phoenix/espi_util.c

@@ -4,7 +4,7 @@
 #include <soc/espi.h>
 #include <types.h>
 
-#define ESPI_CNTRL_REGISTER	0x10
+#define ESPI_CNTRL_REGISTER	0x10 /* SPI register, not eSPI register! */
 #define  LOCK_SPIX10_BIT2	BIT(3)
 #define  ESPI_MUX_SPI1		BIT(2)
 #define  ROM_ADDR_WR_PROT	BIT(1)