mainboard/opencellular/rotundu: Add FMAP support

* Add 8M and 16M fmap configurations.
* Fix kconfig selects.
* Add vboot options and fixes

Change-Id: I49d97a9d324207e45520d43b814b03a20005122a
Signed-off-by: zaolin <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/25084
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
zaolin 2018-03-09 17:27:37 +01:00 committed by Philipp Deppenwiese
parent 2ee7f483b1
commit 0ea7471eec
3 changed files with 84 additions and 4 deletions

View File

@ -18,7 +18,7 @@
config BOARD_OPENCELLULAR_BASEBOARD_ROTUNDU
def_bool n
select SOC_INTEL_FSP_BAYTRAIL
select BOARD_ROMSIZE_KB_16384
select BOARD_ROMSIZE_KB_8192
select HAVE_ACPI_TABLES
select HAVE_OPTION_TABLE
select ENABLE_BUILTIN_COM1
@ -32,6 +32,21 @@ config BOARD_OPENCELLULAR_BASEBOARD_ROTUNDU
if BOARD_OPENCELLULAR_BASEBOARD_ROTUNDU
config VBOOT
select MRC_CACHE_FMAP
select VBOOT_VBNV_CMOS
select VBOOT_NO_BOARD_SUPPORT
select GBB_FLAG_DISABLE_LID_SHUTDOWN
select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC
select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC
select GBB_FLAG_DISABLE_FWMP
config GBB_HWID
string
depends on VBOOT
default "ROTUNDU" if BOARD_OPENCELLULAR_ROTUNDU
default "SUPABRCKV1" if BOARD_OPENCELLULAR_SUPABRCKV1
config VARIANT_DIR
string
default "rotundu" if BOARD_OPENCELLULAR_ROTUNDU
@ -67,11 +82,16 @@ config FSP_LOC
hex
default 0xfffb0000
# FIXME: Slow boot performance when increasing CBFS_SIZE beyond 8MB?
config FMDFILE
string
depends on VBOOT
default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-8M.fmd" if BOARD_ROMSIZE_KB_8192
default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-16M.fmd" if BOARD_ROMSIZE_KB_16384
config CBFS_SIZE
hex
default 0x00200000 if BOARD_ROMSIZE_KB_8192
default 0x00800000
default 0x00140000 if BOARD_ROMSIZE_KB_8192
default 0x003effc0 if BOARD_ROMSIZE_KB_16384
config VIRTUAL_ROM_SIZE
hex

View File

@ -0,0 +1,30 @@
FLASH 16M {
SI_ALL@0x0 0x300000 {
SI_DESC@0x0 0x1000
SI_ME@0x1000 0x2ff000
}
SI_BIOS@0x300000 0xd00000 {
RW_SECTION_B@0x0 0x400000 {
VBLOCK_B@0x0 0x10000
FW_MAIN_B(CBFS)@0x10000 0x3effc0
RW_FWID_B@0x3fffc0 0x40
}
RW_SECTION_A@0x400000 0x400000 {
VBLOCK_A@0x0 0x10000
FW_MAIN_A(CBFS)@0x10000 0x3effc0
RW_FWID_A@0x3fffc0 0x40
}
RW_MRC_CACHE@0x800000 0x10000
RW_VPD@0x810000 0x2000
WP_RO@0x812000 0x4ee000 {
RO_VPD@0x0 0x4000
RO_SECTION@0x4000 0x4ea000 {
FMAP@0x0 0x800
RO_FRID@0x800 0x40
RO_FRID_PAD@0x840 0x7c0
GBB@0x1000 0xef000
COREBOOT(CBFS)@0xf0000 0x3fa000
}
}
}
}

View File

@ -0,0 +1,30 @@
FLASH 8M {
SI_ALL@0x0 0x300000 {
SI_DESC@0x0 0x1000
SI_ME@0x1000 0x2ff000
}
SI_BIOS@0x300000 0x500000 {
RW_SECTION_B@0x0 0x150040 {
VBLOCK_B@0x0 0x10000
FW_MAIN_B(CBFS)@0x10000 0x140000
RW_FWID_B@0x150000 0x40
}
RW_SECTION_A@0x150040 0x150040 {
VBLOCK_A@0x0 0x10000
FW_MAIN_A(CBFS)@0x10000 0x140000
RW_FWID_A@0x150000 0x40
}
RW_MRC_CACHE@0x2a0080 0x10000
RW_VPD@0x2b0080 0x2000
WP_RO@0x2b2080 0x24df80 {
RO_VPD@0x0 0x4000
RO_SECTION@0x4000 0x249f80 {
FMAP@0x0 0x800
RO_FRID@0x800 0x40
RO_FRID_PAD@0x840 0x7c0
GBB@0x1000 0xef000
COREBOOT(CBFS)@0xf0000 0x159f80
}
}
}
}