fsp_broadwell_de: Add ability to set PCIe completion timeout
This enables the user to set the completion timeout value in PCI Express Device Control 2 register via devicetree.cb. Based on corebootBDE-270-iou-complto.patch in Arista EOS 4.20 release. Change-Id: If0527899bc2047d0e57c11f7801768d07f9a5179 Signed-off-by: David Hendricks <dhendricks@fb.com> Reviewed-on: https://review.coreboot.org/26225 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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@ -30,6 +30,7 @@ ramstage-y += smbus.c
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romstage-y += tsc_freq.c
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ramstage-y += smi.c
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ramstage-y += gpio.c
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ramstage-y += iou_complto.c
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ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c
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ramstage-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c
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smm-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c
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@ -23,7 +23,11 @@
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* specified by the devicetree. */
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struct soc_intel_fsp_broadwell_de_config {
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/* PCIe completion timeout value */
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int pcie_compltoval;
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};
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typedef struct soc_intel_fsp_broadwell_de_config config_t;
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extern struct chip_operations soc_intel_fsp_broadwell_de_ops;
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#endif /* _SOC_CHIP_H_ */
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@ -0,0 +1,51 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 Arista Networks, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include <soc/intel/fsp_broadwell_de/chip.h>
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#define DEVCTL2 0xb8
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static void iou_init(struct device *dev)
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{
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const config_t *config = dev->chip_info;
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u16 devctl2;
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/* pcie completion timeout
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EDS Vol 2, Section 7.2.54 */
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devctl2 = pci_read_config16(dev, DEVCTL2);
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devctl2 = (devctl2 & ~0xf) | (config->pcie_compltoval & 0xf);
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pci_write_config16(dev, DEVCTL2, devctl2);
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}
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static struct device_operations iou_ops = {
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.read_resources = pci_bus_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_bus_enable_resources,
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.scan_bus = pci_scan_bridge,
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.reset_bus = pci_bus_reset,
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.init = iou_init,
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};
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static const unsigned short iou_device_ids[] = {
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0x6f02, 0x6f08, 0 };
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static const struct pci_driver iou_driver __pci_driver = {
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.ops = &iou_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.devices = iou_device_ids,
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};
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