mb/asus/p5qc: Add ASUS P5Q as a variant (with documentation)
Change-Id: I6c7bbb89af88cce1a53c21a4b4d8bc1c284e1cb2 Signed-off-by: Ivan Vatlin <jenrus@tuta.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38143 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Ivan Vatlin
Patrick Georgi
parent
16434322ed
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0ebb7840e7
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# ASUS P5Q
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This page describes how to run coreboot on the [ASUS P5Q] desktop board.
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## TODO
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The following things are working in this coreboot port:
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+ PCI slots
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+ PCI-e slots
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+ Onboard Ethernet
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+ USB
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+ Onboard sound card
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+ PS/2 keyboard
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+ All 4 DIMM slots
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+ S3 suspend and resume
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+ Red SATA ports
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The following things are still missing from this coreboot port:
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+ PS/2 mouse support
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+ PATA aka IDE (because of buggy IDE controller)
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+ Fan control (will be working on 100% power)
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+ TPM module (support not implemented)
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The following things are untested on this coreboot port:
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+ S/PDIF
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+ CD Audio In
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+ Floppy disk drive
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+ FireWire: PCI device shows up and driver loads, no further test
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## Flashing coreboot
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```eval_rst
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+-------------------+----------------+
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| Type | Value |
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+===================+================+
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| Socketed flash | Yes |
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+-------------------+----------------+
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| Model | MX25L8005 |
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+-------------------+----------------+
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| Size | 1 MiB |
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+-------------------+----------------+
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| Package | Socketed DIP-8 |
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+-------------------+----------------+
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| Write protection | No |
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+-------------------+----------------+
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| Dual BIOS feature | No |
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+-------------------+----------------+
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| Internal flashing | Yes |
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+-------------------+----------------+
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```
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You can flash coreboot into your motherboard using [this guide].
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## Technology
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```eval_rst
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+------------------+---------------------------------------------------+
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| Northbridge | Intel P45 (called x4x in coreboot code) |
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+------------------+---------------------------------------------------+
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| Southbridge | Intel ICH10R (called i82801jx in coreboot code) |
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+------------------+---------------------------------------------------+
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| CPU (LGA775) | Model f4x, f6x, 6fx, 1067x (Pentium 4, d, Core 2) |
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+------------------+---------------------------------------------------+
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| SuperIO | Winbond W83667HG |
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+------------------+---------------------------------------------------+
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| Coprocessor | No |
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+------------------+---------------------------------------------------+
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| Clockgen (CK505) | ICS 9LPRS918JKLF |
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+------------------+---------------------------------------------------+
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```
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[ASUS P5Q]: https://www.asus.com/Motherboards/P5Q
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[this guide]: https://doc.coreboot.org/flash_tutorial/int_flashrom.html
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@ -1,8 +1,9 @@
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#
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2015 Damien Zammit <damien@zamaudio.com>
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# Copyright (C) 2015 Damien Zammit <damien@zamaudio.com>
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# Copyright (C) 2018 Arthur Heymans <arthur@aheymans.xyz>
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# Copyright (C) 2019 Ivan Vatlin <jenrus@tuta.io>
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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@ -14,7 +15,7 @@
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# GNU General Public License for more details.
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#
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if BOARD_ASUS_P5QC || BOARD_ASUS_P5Q_PRO || BOARD_ASUS_P5QL_PRO
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if BOARD_ASUS_P5QC || BOARD_ASUS_P5Q_PRO || BOARD_ASUS_P5QL_PRO || BOARD_ASUS_P5Q
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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@ -38,12 +39,14 @@ config VARIANT_DIR
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default "p5qc" if BOARD_ASUS_P5QC
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default "p5q_pro" if BOARD_ASUS_P5Q_PRO
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default "p5ql_pro" if BOARD_ASUS_P5QL_PRO
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default "p5q" if BOARD_ASUS_P5Q
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config MAINBOARD_PART_NUMBER
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string
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default "P5QC" if BOARD_ASUS_P5QC
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default "P5Q PRO" if BOARD_ASUS_P5Q_PRO
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default "P5QL PRO" if BOARD_ASUS_P5QL_PRO
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default "P5Q" if BOARD_ASUS_P5Q
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config DEVICETREE
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string
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@ -6,3 +6,6 @@ config BOARD_ASUS_P5Q_PRO
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config BOARD_ASUS_P5QL_PRO
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bool "P5QL PRO"
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config BOARD_ASUS_P5Q
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bool "P5Q"
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@ -0,0 +1,122 @@
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#
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2015 Damien Zammit <damien@zamaudio.com>
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# Copyright (C) 2018 Arthur Heymans <arthur@aheymans.xyz>
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# Copyright (C) 2019 Ivan Vatlin <jenrus@tuta.io>
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; either version 2 of the License, or
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# (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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chip northbridge/intel/x4x # Northbridge
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device cpu_cluster 0 on # APIC cluster
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chip cpu/intel/socket_LGA775
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device lapic 0 on end
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end
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chip cpu/intel/model_1067x # CPU
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device lapic 0xACAC off end
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end
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end
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device domain 0 on # PCI domain
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device pci 0.0 on end # Host Bridge
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device pci 1.0 on end # PEG
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device pci 6.0 off end # PEG 2
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chip southbridge/intel/i82801jx # Southbridge
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register "gpe0_en" = "0x40"
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# Enable all six SATA ports.
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register "sata_port_map" = "0x3f"
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# Enable PCIe ports 0,2,3 as slots.
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register "pcie_slot_implemented" = "0x31"
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register "gen1_dec" = "0x00000295"
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register "gen2_dec" = "0x001c4701"
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device pci 19.0 off end # GBE
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device pci 1a.0 on end # USB
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device pci 1a.1 on end # USB
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device pci 1a.2 on end # USB
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device pci 1a.7 on end # USB
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device pci 1b.0 on end # Audio
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device pci 1c.0 on end # PCIe 1: PCIEX1_1 slot
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device pci 1c.1 on end # PCIe 2: PCIEX1_2 slot
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device pci 1c.2 off end # PCIe 3: Unconnected
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device pci 1c.3 off end # PCIe 4: Unconnected
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device pci 1c.4 on end # PCIe 5: Marvell 88SE6121 IDE/SATA controller
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device pci 1c.5 on end # PCIe 6: Atheros AR8121 Ethernet NIC
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device pci 1d.0 on end # USB
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device pci 1d.1 on end # USB
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device pci 1d.2 on end # USB
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device pci 1d.7 on end # USB
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device pci 1e.0 on end # PCI bridge
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device pci 1f.0 on # LPC bridge
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chip superio/winbond/w83667hg-a # Super I/O
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device pnp 2e.0 on # FDC
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# Global registers
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irq 0x2a = 0x00
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irq 0x2c = 0x22
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irq 0x2d = 0x00
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# Floppy
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io 0x60 = 0x3f0
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irq 0xf0 = 0x0e
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end
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device pnp 2e.1 off end # LPT1
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device pnp 2e.2 on # COM1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.3 off end # COM2
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device pnp 2e.5 on # PS/2 keyboard & mouse
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1
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irq 0x72 = 12
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end
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device pnp 2e.106 off end # SPI1
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device pnp 2e.107 off end # GPIO6
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device pnp 2e.207 off end # GPIO7
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device pnp 2e.307 on # GPIO8
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irq 0xe4 = 0xfb
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end
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device pnp 2e.407 off end # GPIO9
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device pnp 2e.8 off end # WDT
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device pnp 2e.108 off end # GPIO1
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device pnp 2e.9 off end # GPIO2
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device pnp 2e.109 on end # GPIO3
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device pnp 2e.209 on # GPIO4
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irq 0xf0 = 0x7f
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irq 0xfe = 0x07
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end
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device pnp 2e.309 on end # GPIO5
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device pnp 2e.a on # ACPI
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irq 0xe4 = 0x10 # 3VSBSW# enable
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irq 0xe5 = 0x02
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irq 0xf2 = 0xfc
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end
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device pnp 2e.b on # HW Monitor
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io 0x60 = 0x290
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irq 0x70 = 0
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# IRQ purposefully not assigned to prevent lockups
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end
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device pnp 2e.c on end # PECI
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device pnp 2e.d on end # VID_BUSSEL
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device pnp 2e.f on end # GPIO_PP_OD
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end
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end
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device pci 1f.2 on end # SATA
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device pci 1f.3 on end # SMbus
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device pci 1f.4 off end
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device pci 1f.5 off end # SATA (legacy mode)
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device pci 1f.6 off end
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end
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end
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end
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