ec/google: Support ChromeOS EC on SPI bus.
For devices with ChromeOS EC on SPI bus, use the standard SPI driver interface (see spi-generic.h) to exchange data. Note: Only EC protocol v3 is supported for SPI bus. Change-Id: Ia8dcdecd125a2bd7424d0c7560e046b6d6988a03 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/3751 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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@ -22,7 +22,21 @@ config EC_GOOGLE_CHROMEEC_I2C_CHIP
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config EC_GOOGLE_CHROMEEC_LPC
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config EC_GOOGLE_CHROMEEC_LPC
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depends on EC_GOOGLE_CHROMEEC && ARCH_X86 # Needs Plug-and-play.
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depends on EC_GOOGLE_CHROMEEC && ARCH_X86 # Needs Plug-and-play.
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bool
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def_bool y
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default y
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help
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help
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Google Chrome EC via LPC bus.
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Google Chrome EC via LPC bus.
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config EC_GOOGLE_CHROMEEC_SPI
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depends on EC_GOOGLE_CHROMEEC
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def_bool n
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help
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Google's Chrome EC via SPI bus.
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config EC_GOOGLE_CHROMEEC_SPI_BUS
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depends on EC_GOOGLE_CHROMEEC_SPI
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hex "SPI bus for Google's Chrome EC"
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config EC_GOOGLE_CHROMEEC_SPI_CHIP
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depends on EC_GOOGLE_CHROMEEC_SPI
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hex
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default 0
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@ -1,9 +1,12 @@
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ramstage-y += ec.c crosec_proto.c
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ramstage-y += ec.c crosec_proto.c
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ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C) += ec_i2c.c
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ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C) += ec_i2c.c
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ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c
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ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c
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ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SPI) += ec_spi.c
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smm-y += ec.c crosec_proto.c
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smm-y += ec.c crosec_proto.c
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smm-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C) += ec_i2c.c
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smm-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C) += ec_i2c.c
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smm-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c
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smm-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c
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smm-$(CONFIG_EC_GOOGLE_CHROMEEC_SPI) += ec_spi.c
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romstage-y += ec.c crosec_proto.c
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romstage-y += ec.c crosec_proto.c
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romstage-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C) += ec_i2c.c
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romstage-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C) += ec_i2c.c
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romstage-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c
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romstage-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c
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romstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SPI) += ec_spi.c
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@ -0,0 +1,65 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Google Inc. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <spi-generic.h>
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#include "ec.h"
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#include "ec_commands.h"
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#define CROSEC_SPI_SPEED (500000)
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static int crosec_spi_io(uint8_t *write_bytes, size_t write_size,
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uint8_t *read_bytes, size_t read_size,
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void *context)
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{
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struct spi_slave *slave = (struct spi_slave *)context;
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int rv;
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spi_claim_bus(slave);
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rv = spi_xfer(slave, write_bytes, write_size * 8, read_bytes,
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read_size * 8);
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spi_release_bus(slave);
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if (rv != 0) {
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printk(BIOS_ERR, "%s: Cannot complete SPI I/O\n", __func__);
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return -1;
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}
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return 0;
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}
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int google_chromeec_command(struct chromeec_command *cec_command)
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{
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static struct spi_slave *slave = NULL;
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if (!slave) {
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slave = spi_setup_slave(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS,
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CONFIG_EC_GOOGLE_CHROMEEC_SPI_CHIP,
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CROSEC_SPI_SPEED,
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SPI_READ_FLAG | SPI_WRITE_FLAG);
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}
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return crosec_command_proto(cec_command, crosec_spi_io, slave);
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}
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#ifndef __PRE_RAM__
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u8 google_chromeec_get_event(void)
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{
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printk(BIOS_ERR, "%s: Not supported.\n", __func__);
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return 0;
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}
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#endif
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