GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

haswell: use new interface to disable rom caching 

The haswell code was using the old assumption of which MTRR
was used for the ROM cache. Now that there is an API for doing
this use it as the old assumption is no longer valid.

Change-Id: I59ef897becfc9834d36d28840da6dc4f1145b0c7
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3007
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Aaron Durbin 2013-04-01 15:40:45 -05:00 committed by Stefan Reinauer
parent d46161e9ea
commit 0f0fe100cb
1 changed files with 1 additions and 22 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

23
src/cpu/intel/haswell/mp_init.c
View File

@ -145,28 +145,7 @@ void release_aps_for_smm_relocation(int do_parallel)
* ensure the caching is disabled for tha APs before going to sleep. */
static void cleanup_rom_caching(void)
{
#if CONFIG_CACHE_ROM
msr_t msr;
unsigned int last_var_mtrr;
msr = rdmsr(MTRRcap_MSR);
last_var_mtrr = (msr.lo & 0xff) - 1;
/* Check if the MTRR is valid. */
msr = rdmsr(MTRRphysMask_MSR(last_var_mtrr));
if ((msr.lo & MTRRphysMaskValid) == 0)
return;
msr = rdmsr(MTRRphysBase_MSR(last_var_mtrr));
/* Assum that if the MTRR is of write protected type, the MTRR is used
* to cache the ROM. */
if ((msr.lo & MTRR_NUM_TYPES) == MTRR_TYPE_WRPROT) {
msr.lo = msr.hi = 0;
disable_cache();
wrmsr(MTRRphysMask_MSR(last_var_mtrr), msr);
wrmsr(MTRRphysBase_MSR(last_var_mtrr), msr);
enable_cache();
}
#endif
x86_mtrr_disable_rom_caching();
}
/* By the time APs call ap_init() caching has been setup, and microcode has