vendorcode/amd/agesa: Drop unused common code

No platform uses this.

Change-Id: If32a4de7ef263f1d4f7ab7a36751ad9dcf52dc7e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69127
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Arthur Heymans 2022-11-02 00:14:06 +01:00
parent 7036ded25d
commit 0f12381083
10 changed files with 0 additions and 2203 deletions

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@ -1,3 +1,2 @@
subdirs-y += pi
subdirs-y += agesa
subdirs-y += cimx

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@ -1,182 +0,0 @@
# SPDX-License-Identifier: GPL-2.0-only
config IDS_OPTIONS_HOOKED_UP
bool
help
to Kconfig options.
Historically, IDS configuration was defined in a mainboard-specific
`OptionsIds.h` header. Select this on platforms where IDS config is
hooked up to Kconfig options instead.
if IDS_OPTIONS_HOOKED_UP
config IDS_ENABLED
bool "Enable AGESA IDS (Integrated Debug Services) support"
default y
help
This is the master switch for the IDS sub-system. Use this option to
enable or remove the entire IDS feature set. This switch must be TRUE
for any of the other options to function.
comment "Warning: IDS options may not work. Enable at your own risk!"
depends on IDS_ENABLED
config IDS_CONTROL_ENABLED
bool "Enable IDS User Interface controls"
depends on IDS_ENABLED
help
This is the main switch for the IDS configuration controls. This
switch must be TRUE for any of the configuration controls to function.
This seems to allow AGESA to retrieve settings from CMOS.
config IDS_PERF_ANALYSIS
bool "Enable IDS performance analysis"
depends on IDS_ENABLED
help
This is the main switch for the IDS performance analysis controls,
macros and support code needed to enable time data gathering. This
switch must be TRUE for any of the performance analysis features to
function.
config IDS_TRACING_ENABLED
bool "Enable IDS console"
depends on IDS_ENABLED
help
This is the main switch for the IDS console controls, macros and
support code needed to enable tracing of algorithms. This switch
must be TRUE for any of the tracing features to function.
config IDS_TRACING_CONSOLE_SERIAL
bool "Use serial port as IDS console"
depends on IDS_TRACING_ENABLED
default DRIVERS_UART_8250IO && CONSOLE_SERIAL
help
Use an I/O-mapped serial port to output IDS messages.
endif # IDS_OPTIONS_HOOKED_UP
choice
prompt "DDR3 memory profile"
default CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC
help
Choose the DDR3 memory profile to use for your RAM sticks, e.g. XMP 1.
XMP support is experimental, and your PC will fail booting if you choose
a profile which does not exist on ANY of your RAM sticks! If in doubt
check their SPD Data using a coreboot's great fork of memtest86+ 5.01.
config CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC
bool "JEDEC"
help
JEDEC memory profile, standard and stable. Is guaranteed to be working.
config CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_1
bool "XMP 1"
help
XMP 1 memory profile. Check that it exists on ALL of your RAM sticks!
config CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_2
bool "XMP 2"
help
XMP 2 memory profile. Check that it exists on ALL of your RAM sticks!
config CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM
bool "CUSTOM"
help
Custom memory profile. Use the XMP SPD values as the base, if available.
endchoice
if CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM
config CUSTOM_SPD_DIVIDENT
int "[10]: Medium Timebase (MTB) Dividend"
default 1
range 1 255
config CUSTOM_SPD_DIVISOR
int "[11]: Medium Timebase (MTB) Divisor"
default 14
range 1 255
config CUSTOM_SPD_TCK
int "[12]: SDRAM Minimum Cycle Time, tCK"
default 15
range 1 255
config CUSTOM_SPD_CASLO
int "[14]: CAS Latencies Supported, Lower Byte"
default 124
range 0 255
config CUSTOM_SPD_CASHI
int "[15]: CAS Latencies Supported, Higher Byte"
default 0
range 0 255
config CUSTOM_SPD_TAA
int "[16]: Min CAS Latency Time, tAA"
default 132
range 1 255
config CUSTOM_SPD_TWR
int "[17]: Min Write Recovery Time, tWR"
default 210
range 1 255
config CUSTOM_SPD_TRCD
int "[18]: Min RAS# to CAS# Delay Time, tRCD"
default 132
range 1 255
config CUSTOM_SPD_TRRD
int "[19]: Min Row Active to Row Active Delay Time, tRRD"
default 84
range 1 255
config CUSTOM_SPD_TRP
int "[20]: Min Row Precharge Delay Time, tRP"
default 132
range 1 255
config CUSTOM_SPD_UPPER_TRC
int "[21][7:4]: Min Active to Active/Refresh Delay, UPPER tRC"
default 2
range 0 16
config CUSTOM_SPD_UPPER_TRAS
int "[21][3:0]: Min Active to Precharge Delay Time, UPPER tRAS"
default 1
range 0 16
config CUSTOM_SPD_TRAS
int "[22]: Min Active to Precharge Delay Time, LOWER tRAS"
default 138
range 1 255
config CUSTOM_SPD_TRC
int "[23]: Min Active to Active/Refresh Delay, LOWER tRC"
default 181
range 1 255
config CUSTOM_SPD_TWTR
int "[26]: Min Internal Write to Read Command Delay, tWTR"
default 105
range 1 255
config CUSTOM_SPD_TRTP
int "[27]: Min Internal Read to Precharge Command Delay, tRTP"
default 105
range 1 255
config CUSTOM_SPD_UPPER_TFAW
int "[28][3:0]: Min Four Activate Window Delay, UPPER tFAW"
default 1
range 0 16
config CUSTOM_SPD_TFAW
int "[29]: Min Four Activate Window Delay Time, tFAW"
default 164
range 1 255
endif

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@ -1,41 +0,0 @@
ifeq ($(CONFIG_CPU_AMD_AGESA),y)
subdirs-y += common
classes-y += libagesa
libagesa-y =
libagesa-generic-ccopts += -D__LIBAGESA__
libagesa-generic-ccopts += $(AGESA_INC) $(AGESA_AUTOINCLUDES)
libagesa-generic-ccopts += -Wno-pragma-pack -Wno-unused-but-set-variable
libagesa-generic-ccopts += -Wno-implicit-fallthrough
romstage-generic-ccopts += -Wno-pragma-pack
ramstage-generic-ccopts += -Wno-pragma-pack
AGESA_CFLAGS := -march=k8-sse3 -mtune=k8-sse3 -fno-strict-aliasing
CFLAGS_x86_32 += $(AGESA_CFLAGS)
CFLAGS_x86_64 += $(AGESA_CFLAGS)
ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y)
$(eval $(call create_class_compiler,libagesa,x86_32))
else
$(eval $(call create_class_compiler,libagesa,x86_64))
endif
$(obj)/libagesa.a: $$(libagesa-objs)
@printf " AGESA $(subst $(obj)/,,$(@))\n"
$(AR_libagesa) rcsDT $@ $+
romstage-libs += $(obj)/libagesa.a
ramstage-libs += $(obj)/libagesa.a
# buildOpts should be in libagesa
$(obj)/romstage/mainboard/$(MAINBOARDDIR)/buildOpts.o: CPPFLAGS_x86_32 += $(BUILDOPTS_INCLUDES)
$(obj)/ramstage/mainboard/$(MAINBOARDDIR)/buildOpts.o: CPPFLAGS_x86_32 += $(BUILDOPTS_INCLUDES)
$(obj)/romstage/vendorcode/amd/agesa/common/agesa-entry.o: CPPFLAGS_x86_32 += $(BUILDOPTS_INCLUDES)
$(obj)/ramstage/vendorcode/amd/agesa/common/agesa-entry.o: CPPFLAGS_x86_32 += $(BUILDOPTS_INCLUDES)
endif

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@ -1,36 +0,0 @@
#*****************************************************************************
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
# * Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# * Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# * Neither the name of Advanced Micro Devices, Inc. nor the names of
# its contributors may be used to endorse or promote products derived
# from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
# DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
#*****************************************************************************
romstage-y += agesa-entry.c
ramstage-y += agesa-entry.c
libagesa-y += debug_util.c
libagesa-y += amdlib.c
# Do not optimise performance-critical low-level IO for size with -Os,
# request -O2 with -falign-functions.
$(obj)/libagesa/vendorcode/amd/agesa/common/amdlib.o: CFLAGS_libagesa += -O2

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@ -1,82 +0,0 @@
#ifndef AGESA_ENTRY_CFG_H
#define AGESA_ENTRY_CFG_H
#if ENV_RAMINIT
#define AGESA_ENTRY_INIT_RESET TRUE
#define AGESA_ENTRY_INIT_EARLY TRUE
#define AGESA_ENTRY_INIT_POST TRUE
#define AGESA_ENTRY_INIT_RESUME CONFIG(HAVE_ACPI_RESUME)
#else
#define AGESA_ENTRY_INIT_ENV TRUE
#define AGESA_ENTRY_INIT_LATE_RESTORE CONFIG(HAVE_ACPI_RESUME)
#define AGESA_ENTRY_INIT_MID TRUE
#define AGESA_ENTRY_INIT_LATE TRUE
#define AGESA_ENTRY_INIT_S3SAVE \
(CONFIG(HAVE_ACPI_RESUME) || \
CONFIG(ENABLE_MRC_CACHE))
#endif
/* Not required. */
#define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE
/* Required for any multi-core. */
#define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE
/* Deprecated, reference source is removed from the tree. */
#define AGESA_ENTRY_INIT_RECOVERY FALSE
/* Defaults below. */
/* Process user desired AGESA entry points */
#ifndef AGESA_ENTRY_INIT_RESET
#define AGESA_ENTRY_INIT_RESET FALSE
#endif
#ifndef AGESA_ENTRY_INIT_EARLY
#define AGESA_ENTRY_INIT_EARLY FALSE
#endif
#ifndef AGESA_ENTRY_INIT_POST
#define AGESA_ENTRY_INIT_POST FALSE
#endif
#ifndef AGESA_ENTRY_INIT_ENV
#define AGESA_ENTRY_INIT_ENV FALSE
#endif
#ifndef AGESA_ENTRY_INIT_MID
#define AGESA_ENTRY_INIT_MID FALSE
#endif
#ifndef AGESA_ENTRY_INIT_LATE
#define AGESA_ENTRY_INIT_LATE FALSE
#endif
#ifndef AGESA_ENTRY_INIT_S3SAVE
#define AGESA_ENTRY_INIT_S3SAVE FALSE
#endif
#ifndef AGESA_ENTRY_INIT_RESUME
#define AGESA_ENTRY_INIT_RESUME FALSE
#endif
#ifndef AGESA_ENTRY_INIT_LATE_RESTORE
#define AGESA_ENTRY_INIT_LATE_RESTORE FALSE
#endif
#ifndef AGESA_ENTRY_INIT_GENERAL_SERVICES
#define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE
#endif
#ifndef AGESA_ENTRY_LATE_RUN_AP_TASK
#define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE
#endif
#endif /* AGESA_ENTRY_CFG_H */

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@ -1,165 +0,0 @@
#include <Porting.h>
#include <AMD.h>
#include <AGESA.h>
#include "CommonReturns.h"
#include <heapManager.h>
#include <CreateStruct.h>
#include <Options.h>
#include <agesa-entry-cfg.h>
CONST FUNCTION_PARAMS_INFO ROMDATA FuncParamsInfo[] =
{
#if AGESA_ENTRY_INIT_RESET == TRUE
{ AMD_INIT_RESET,
sizeof (AMD_RESET_PARAMS),
(PF_AGESA_FUNCTION) AmdInitResetConstructor,
(PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
AMD_INIT_RESET_HANDLE
},
#endif
#if AGESA_ENTRY_INIT_EARLY == TRUE
{ AMD_INIT_EARLY,
sizeof (AMD_EARLY_PARAMS),
(PF_AGESA_FUNCTION) AmdInitEarlyInitializer,
(PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
AMD_INIT_EARLY_HANDLE
},
#endif
#if AGESA_ENTRY_INIT_ENV == TRUE
{ AMD_INIT_ENV,
sizeof (AMD_ENV_PARAMS),
(PF_AGESA_FUNCTION) AmdInitEnvInitializer,
(PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
AMD_INIT_ENV_HANDLE
},
#endif
#if AGESA_ENTRY_INIT_LATE == TRUE
{ AMD_INIT_LATE,
sizeof (AMD_LATE_PARAMS),
(PF_AGESA_FUNCTION) AmdInitLateInitializer,
(PF_AGESA_DESTRUCTOR) AmdInitLateDestructor,
AMD_INIT_LATE_HANDLE
},
#endif
#if AGESA_ENTRY_INIT_MID == TRUE
{ AMD_INIT_MID,
sizeof (AMD_MID_PARAMS),
(PF_AGESA_FUNCTION) AmdInitMidInitializer,
(PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
AMD_INIT_MID_HANDLE
},
#endif
#if AGESA_ENTRY_INIT_POST == TRUE
{ AMD_INIT_POST,
sizeof (AMD_POST_PARAMS),
(PF_AGESA_FUNCTION) AmdInitPostInitializer,
(PF_AGESA_DESTRUCTOR) AmdInitPostDestructor,
AMD_INIT_POST_HANDLE
},
#endif
#if AGESA_ENTRY_INIT_RESUME == TRUE
{ AMD_INIT_RESUME,
sizeof (AMD_RESUME_PARAMS),
(PF_AGESA_FUNCTION) AmdInitResumeInitializer,
(PF_AGESA_DESTRUCTOR) AmdInitResumeDestructor,
AMD_INIT_RESUME_HANDLE
},
#endif
#if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
{ AMD_S3LATE_RESTORE,
sizeof (AMD_S3LATE_PARAMS),
(PF_AGESA_FUNCTION) AmdS3LateRestoreInitializer,
(PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
AMD_S3_LATE_RESTORE_HANDLE
},
#endif
#if AGESA_ENTRY_INIT_S3SAVE == TRUE
{ AMD_S3_SAVE,
sizeof (AMD_S3SAVE_PARAMS),
(PF_AGESA_FUNCTION) AmdS3SaveInitializer,
(PF_AGESA_DESTRUCTOR) AmdS3SaveDestructor,
AMD_S3_SAVE_HANDLE
},
#endif
#if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE
{ AMD_LATE_RUN_AP_TASK,
sizeof (AP_EXE_PARAMS),
(PF_AGESA_FUNCTION) AmdLateRunApTaskInitializer,
(PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
AMD_LATE_RUN_AP_TASK_HANDLE
},
#endif
{ 0, 0, NULL }
};
CONST UINTN InitializerCount = ARRAY_SIZE(FuncParamsInfo);
CONST DISPATCH_TABLE ROMDATA DispatchTable[] =
{
{ AMD_CREATE_STRUCT, (IMAGE_ENTRY)AmdCreateStruct },
{ AMD_RELEASE_STRUCT, (IMAGE_ENTRY)AmdReleaseStruct },
#if AGESA_ENTRY_INIT_RESET == TRUE
{ AMD_INIT_RESET, (IMAGE_ENTRY)AmdInitReset },
#endif
#if AGESA_ENTRY_INIT_EARLY == TRUE
{ AMD_INIT_EARLY, (IMAGE_ENTRY)AmdInitEarly },
#endif
#if AGESA_ENTRY_INIT_POST == TRUE
{ AMD_INIT_POST, (IMAGE_ENTRY)AmdInitPost },
#endif
#if AGESA_ENTRY_INIT_ENV == TRUE
{ AMD_INIT_ENV, (IMAGE_ENTRY)AmdInitEnv },
#endif
#if AGESA_ENTRY_INIT_MID == TRUE
{ AMD_INIT_MID, (IMAGE_ENTRY)AmdInitMid },
#endif
#if AGESA_ENTRY_INIT_LATE == TRUE
{ AMD_INIT_LATE, (IMAGE_ENTRY)AmdInitLate },
#endif
#if AGESA_ENTRY_INIT_S3SAVE == TRUE
{ AMD_S3_SAVE, (IMAGE_ENTRY)AmdS3Save },
#endif
#if AGESA_ENTRY_INIT_RESUME == TRUE
{ AMD_INIT_RESUME, (IMAGE_ENTRY)AmdInitResume },
#endif
#if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
{ AMD_S3LATE_RESTORE, (IMAGE_ENTRY)AmdS3LateRestore },
#endif
{ AMD_READ_EVENT_LOG, (IMAGE_ENTRY)AmdReadEventLog },
#if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE
{ AMD_GET_APIC_ID, (IMAGE_ENTRY)AmdGetApicId },
{ AMD_GET_PCI_ADDRESS, (IMAGE_ENTRY)AmdGetPciAddress },
{ AMD_IDENTIFY_CORE, (IMAGE_ENTRY)AmdIdentifyCore },
{ AMD_IDENTIFY_DIMMS, (IMAGE_ENTRY)AmdIdentifyDimm },
{ AMD_GET_EXECACHE_SIZE, (IMAGE_ENTRY)AmdGetAvailableExeCacheSize },
#endif
#if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE
{ AMD_LATE_RUN_AP_TASK, (IMAGE_ENTRY)AmdLateRunApTask },
#endif
{ 0, NULL }
};

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@ -1,398 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Library
*
* Contains interface to the AMD AGESA library
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Lib
* @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#ifndef _AMD_LIB_H_
#define _AMD_LIB_H_
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
#define IOCF8 0xCF8
#define IOCFC 0xCFC
// Reg Values for ReadCpuReg and WriteCpuReg
#define CR0_REG 0x00
#define CR4_REG 0x04
#define DR0_REG 0x10
#define DR1_REG 0x11
#define DR2_REG 0x12
#define DR3_REG 0x13
#define DR7_REG 0x17
UINT8
ReadIo8 (
IN UINT16 Address
);
UINT16
ReadIo16 (
IN UINT16 Address
);
UINT32
ReadIo32 (
IN UINT16 Address
);
VOID
WriteIo8 (
IN UINT16 Address,
IN UINT8 Data
);
VOID
WriteIo16 (
IN UINT16 Address,
IN UINT16 Data
);
VOID
WriteIo32 (
IN UINT16 Address,
IN UINT32 Data
);
UINT8
Read64Mem8 (
IN UINT64 Address
);
UINT16
Read64Mem16 (
IN UINT64 Address
);
UINT32
Read64Mem32 (
IN UINT64 Address
);
VOID
Write64Mem8 (
IN UINT64 Address,
IN UINT8 Data
);
VOID
Write64Mem16 (
IN UINT64 Address,
IN UINT16 Data
);
VOID
Write64Mem32 (
IN UINT64 Address,
IN UINT32 Data
);
UINT64
ReadTSC (
VOID
);
// MSR
VOID
LibAmdMsrRead (
IN UINT32 MsrAddress,
OUT UINT64 *Value,
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
VOID
LibAmdMsrWrite (
IN UINT32 MsrAddress,
CONST IN UINT64 *Value,
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
// IO
VOID
LibAmdIoRead (
IN ACCESS_WIDTH AccessWidth,
IN UINT16 IoAddress,
OUT VOID *Value,
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
VOID
LibAmdIoWrite (
IN ACCESS_WIDTH AccessWidth,
IN UINT16 IoAddress,
IN CONST VOID *Value,
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
VOID
LibAmdIoRMW (
IN ACCESS_WIDTH AccessWidth,
IN UINT16 IoAddress,
IN CONST VOID *Data,
IN CONST VOID *DataMask,
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
VOID
LibAmdIoPoll (
IN ACCESS_WIDTH AccessWidth,
IN UINT16 IoAddress,
IN CONST VOID *Data,
IN CONST VOID *DataMask,
IN UINT64 Delay,
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
// Memory or MMIO
VOID
LibAmdMemRead (
IN ACCESS_WIDTH AccessWidth,
IN UINT64 MemAddress,
OUT VOID *Value,
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
VOID
LibAmdMemWrite (
IN ACCESS_WIDTH AccessWidth,
IN UINT64 MemAddress,
IN CONST VOID *Value,
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
VOID
LibAmdMemRMW (
IN ACCESS_WIDTH AccessWidth,
IN UINT64 MemAddress,
IN CONST VOID *Data,
IN CONST VOID *DataMask,
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
VOID
LibAmdMemPoll (
IN ACCESS_WIDTH AccessWidth,
IN UINT64 MemAddress,
IN CONST VOID *Data,
IN CONST VOID *DataMask,
IN UINT64 Delay,
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
// PCI
VOID
LibAmdPciRead (
IN ACCESS_WIDTH AccessWidth,
IN PCI_ADDR PciAddress,
OUT VOID *Value,
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
VOID
LibAmdPciWrite (
IN ACCESS_WIDTH AccessWidth,
IN PCI_ADDR PciAddress,
IN CONST VOID *Value,
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
VOID
LibAmdPciRMW (
IN ACCESS_WIDTH AccessWidth,
IN PCI_ADDR PciAddress,
IN CONST VOID *Data,
IN CONST VOID *DataMask,
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
VOID
LibAmdPciPoll (
IN ACCESS_WIDTH AccessWidth,
IN PCI_ADDR PciAddress,
IN CONST VOID *Data,
IN CONST VOID *DataMask,
IN UINT64 Delay,
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
VOID
LibAmdPciReadBits (
IN PCI_ADDR Address,
IN UINT8 Highbit,
IN UINT8 Lowbit,
OUT UINT32 *Value,
IN AMD_CONFIG_PARAMS *StdHeader
);
VOID
LibAmdPciWriteBits (
IN PCI_ADDR Address,
IN UINT8 Highbit,
IN UINT8 Lowbit,
IN CONST UINT32 *Value,
IN AMD_CONFIG_PARAMS *StdHeader
);
VOID
LibAmdPciFindNextCap (
IN OUT PCI_ADDR *Address,
IN AMD_CONFIG_PARAMS *StdHeader
);
// CPUID
VOID
LibAmdCpuidRead (
IN UINT32 CpuidFcnAddress,
OUT CPUID_DATA *Value,
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
// Utility Functions
VOID
LibAmdMemFill (
IN VOID *Destination,
IN UINT8 Value,
IN UINTN FillLength,
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
VOID
LibAmdMemCopy (
IN VOID *Destination,
IN CONST VOID *Source,
IN UINTN CopyLength,
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
UINT32
LibAmdGetPackageType (
IN AMD_CONFIG_PARAMS *StdHeader
);
UINT8
LibAmdBitScanReverse (
IN UINT32 value
);
UINT8
LibAmdBitScanForward (
IN UINT32 value
);
VOID
LibAmdReadCpuReg (
IN UINT8 RegNum,
OUT UINT32 *Value
);
VOID
LibAmdWriteCpuReg (
IN UINT8 RegNum,
IN UINT32 Value
);
VOID
LibAmdWriteBackInvalidateCache (
IN VOID
);
VOID
LibAmdSimNowEnterDebugger (VOID);
VOID
LibAmdHDTBreakPoint (VOID);
UINT8
LibAmdAccessWidth (
IN ACCESS_WIDTH AccessWidth
);
VOID
LibAmdCLFlush (
IN UINT64 Address,
IN UINT8 Count
);
VOID F10RevDProbeFilterCritical (
IN PCI_ADDR PciAddress,
IN UINT32 PciRegister
);
VOID
LibAmdFinit (
VOID
);
VOID
StopHere (
VOID
);
/* For f14 or older. */
VOID
CpuidRead (
IN UINT32 CpuidFcnAddress,
OUT CPUID_DATA *Value
);
UINT8
ReadNumberOfCpuCores(
VOID
);
/* From 16kb, no implementation supplied. */
VOID
LibAmdFnclex (
VOID);
VOID
LibAmdReadMxcsr (
OUT UINT32 *Value
);
VOID
LibAmdWriteMxcsr (
IN UINT32 *Value
);
#endif // _AMD_LIB_H_

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@ -1,24 +0,0 @@
#include <AGESA.h>
#include <AMD.h>
#include <heapManager.h>
#include "debug_util.h"
static const char undefined[] = "undefined";
static const char *HeapStatusStr[] = {
"DoNotExistYet", "LocalCache", "TempMem", "SystemMem", "DoNotExistAnymore","S3Resume"
};
/* This function has to match with enumeration of XXXX defined
* inside heapManager.h header file.
*/
const char *heap_status_name(UINT8 HeapStatus)
{
if ((HeapStatus < HEAP_DO_NOT_EXIST_YET) || (HeapStatus > HEAP_S3_RESUME))
return undefined;
int index = HeapStatus - HEAP_DO_NOT_EXIST_YET;
return HeapStatusStr[index];
}

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#ifndef __AGESA_DEBUG_UTIL_H__
#define __AGESA_DEBUG_UTIL_H__
#include "AMD.h"
const char *heap_status_name(UINT8 HeapStatus);
#endif